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2017-01-10H.264 encoder: add a simple reactive VBR rate control modeHEADmasterMark Thompson5-20/+141
This implements a simple reactive VBR rate control mode for single-layer H.264. The primary aim here is to avoid the problematic behaviour that the CBR rate controller displays on scene changes, where the QP can get pushed up by a large amount in a short period and compromise the quality of following frames to a very visible degree. The main idea, then, is to try to keep the HRD buffering above the target level most of the time, so that when a large frame is generated (on a scene change or when the stream complexity increases) we have plenty of slack to be able to encode the more difficult region without compromising quality immediately on the following frames. It is optimistic about the complexity of future frames, so even after generating one or more large frames on a significant change it will try to keep the QP at its current level until the HRD buffer bounds force a change to maintain the intended rate. Compared to the CBR rate controller, it keeps the quality level much more stable - QP does not always spike up as large frames are generated when the complexity of the stream increases transiently, but equally it does not reduce as quickly when the complexity of the stream decreases. Signed-off-by: Mark Thompson <sw@jkqxz.net>
2017-01-091.8.0.pre1 for developmentXiang, Haihao1-2/+2
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2017-01-09Merge branch 'v1.7-branch' into fdo--masterXiang, Haihao2-2/+13
Conflicts: configure.ac src/gen6_mfc.h src/gen6_mfc_common.c src/gen75_picture_process.c src/gen75_vpp_vebox.h src/gen8_mfc.c src/gen9_mfc_hevc.c src/gen9_vdenc.c src/gen9_vme.c src/gen9_vp9_encoder.c src/i965_drv_video.c src/i965_drv_video.h src/i965_encoder.c src/i965_encoder.h src/intel_driver.c src/intel_driver.h test/i965_avcd_config_test.cpp test/i965_avce_config_test.cpp test/i965_jpegd_config_test.cpp test/i965_jpege_config_test.cpp
2017-01-05Encoder: release all misc parameter buffersXiang, Haihao1-10/+5
User can still use the old setting if needed because the setting is stored in a common structure now. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Mark Thompson <sw@jkqxz.net> Tested-by: Mark Thompson <sw@jkqxz.net>
2017-01-05AVC encoder: use generic ROI parametersXiang, Haihao1-40/+20
Presently ROI parameters are stored in the common structure, each codec can use these parameters. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2017-01-05H.264 encoder: respect initial QP settingMark Thompson3-9/+18
Signed-off-by: Mark Thompson <sw@jkqxz.net> Reviewed-by: Xiang, Haihao<haihao.xiang@intel.com>
2017-01-05H.264 encoder: respect min QP settingMark Thompson3-13/+20
Signed-off-by: Mark Thompson <sw@jkqxz.net> Reviewed-by: Xiang, Haihao<haihao.xiang@intel.com>
2016-12-30Initialize some buffers to 0 when createdXiang, Haihao1-2/+6
Sometimes user doesn't assign a proper value to each field in a buffer when calling vaRenderPicture(), which will result in random issues if we want to use these fields in the future. E.g. recently we used window_size in VAEncMiscParameterRateControl for bitrate control. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2016-12-29Needn't reset brc if the bitrate setting isn't changed in the ↵Xiang, Haihao1-28/+44
Begin/Render/End sequence User can use VAEncMiscParameterRateControl to update bitrate, so we should ignore the bitrate in the sequence parameter if VAEncMiscParameterRateControl is present. Hence it is not needed to reset brc if VAEncMiscParameterRateControl doesn't change the used bitrate. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2016-12-29Add new sequence flag check for HEVC/VP9 EncodingZhao Yakui1-0/+17
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Reviewed-by: Xiang, Haihao<haihao.xiang@intel.com>
2016-12-28Support AVC VDEnc on KBLXiang, Haihao4-18/+224
I verified AVC VDEnc on KBL with the HuC loading patch from https://patchwork.freedesktop.org/api/1.0/series/16584/revisions/1/mbox/ Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Kelley, Sean V <sean.v.kelley@intel.com> Tested-by: Tang, FuweiX <fuweix.tang@intel.com>
2016-12-28Enable AVC VDEnc on BXTXiang, Haihao1-0/+3
I verified AVC VDEnc with the HuC loading patch from https://patchwork.freedesktop.org/api/1.0/series/16584/revisions/1/mbox/ Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Tested-by: Tang, FuweiX <fuweix.tang@intel.com>
2016-12-28VDEnc: update the constant bufferXiang, Haihao1-3/+3
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Kelley, Sean V <sean.v.kelley@intel.com>
2016-12-28VDEnc: update the value of inter rounding for CQP modeXiang, Haihao1-1/+5
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Kelley, Sean V <sean.v.kelley@intel.com>
2016-12-28VDEnc: update the MFX_AVC_IMG_STATE commandXiang, Haihao1-4/+5
Don't enable brc domain rate control if HuC is not used. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Kelley, Sean V <sean.v.kelley@intel.com>
2016-12-28VDEnc: always enable bitrate control per mbXiang, Haihao1-0/+1
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Kelley, Sean V <sean.v.kelley@intel.com>
2016-12-23VP9 encoder: use generic rate control parametersMark Thompson5-222/+69
Also adds support for fractional framerate. Signed-off-by: Mark Thompson <sw@jkqxz.net> Reviewed-by: Xiang, Haihao<haihao.xiang@intel.com>
2016-12-23VP8 encoder: use generic rate control parametersMark Thompson2-62/+17
Signed-off-by: Mark Thompson <sw@jkqxz.net> Reviewed-by: Xiang, Haihao<haihao.xiang@intel.com>
2016-12-23HEVC encoder: use generic rate control parametersMark Thompson3-79/+84
Signed-off-by: Mark Thompson <sw@jkqxz.net> Reviewed-by: Xiang, Haihao<haihao.xiang@intel.com>
2016-12-23i965_encoder: consistently represent framerate as a fractionMark Thompson5-33/+65
Update references in both H.264 encoders (gen6_mfc and gen9_vdenc). Signed-off-by: Mark Thompson <sw@jkqxz.net> Reviewed-by: Xiang, Haihao<haihao.xiang@intel.com>
2016-12-15H.265 main 10 encoder supports only 10bpp render targetsMark Thompson1-0/+2
Signed-off-by: Mark Thompson <sw@jkqxz.net> Reviewed-by: Sean V Kelley <seanvk@posteo.de>
2016-12-02Check VP8 brc parameters in the common functionXiang, Haihao1-0/+59
These parameters are irrelative to platforms Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2016-11-30Add a function table for used GPE functionsXiang, Haihao5-2/+173
It is useful for sharing GPE based code between different platforms Currently it is available on GEN8+ Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2016-11-30Rename gen9_gpe_mi_load_register_xxx() to gen8_gpe_mi_load_register_xxx()Xiang, Haihao3-7/+7
xxx is mem/imm/reg and the 3 functions can be used for GEN8 too Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2016-11-30Don't parse Misc parameters in VDEncXiang, Haihao1-127/+31
Instead we can use the parameters saved in the common encoder context. It also corrects frame rate used in VDEnc v2: Align the ROI region and fix compile error after rebase Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2016-11-30Save other bitrate control parameters in the common encoder contextpeng.chen2-1/+15
These parameters can be used for all codecs v2: Save mb_rate_control/target_percentage per layer too Signed-off-by: peng.chen <peng.c.chen@intel.com> Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2016-11-30Save ROI parameters in the common encoder contextpeng.chen2-0/+41
These parameters can be used for all codecs v2: Don't align ROI region, each codec might have special requirement Signed-off-by: peng.chen <peng.c.chen@intel.com> Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2016-11-29Rewrite Media_kernel to optimize the YUV420 8Bit-scaling on Gen8Zhao Yakui5-2/+832
The following conversion is supported: NV12->NV12 NV12->I420 I420->NV12 I420->I420 Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Reviewed-by: Xiang, Haihao<haihao.xiang@intel.com>
2016-11-29Rewrite Media_kernel to optimize the YUV420 8Bit-scaling on Gen9+Zhao Yakui10-8/+891
V1->V2: Add the support of clearing background color for NV12 The following conversion is supported: NV12->NV12 NV12->I420 I420->NV12 I420->I420 Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Reviewed-by: Xiang, Haihao<haihao.xiang@intel.com>
2016-11-29Move some VPP structures/functions into the common files to support more ↵Zhao Yakui6-40/+121
platforms This is to define some common structures/functions so that they can be used on more platforms when adding new VPP functions. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Reviewed-by: Xiang, Haihao<haihao.xiang@intel.com>
2016-11-22i965_GetDisplayAttributes: propagate flags from src to dstDaniel Charles1-0/+5
flags need to be propagated for user to know which flags are supported by VADisplayAttribType. When only VA_DISPLAY_ATTRIB_SETTABLE is reported as flag then it has to be propagated back to user. The rest of the values should be left untouched Signed-off-by: Daniel Charles <daniel.charles@intel.com>
2016-11-21Add the 10bit-scaling conversion for I010 formatZhao Yakui1-3/+42
I010 format is another kind of 10-bit surface. And its layout is similar to I420. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2016-11-21Add the support of 10bit I010 surfaceZhao Yakui2-0/+27
And it is treated as non-tiling for I010 surfaces, which is like I420. Every pixel also uses two bytes like P010 but it occupies the lower 10-bit. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2016-11-21Use obtained eu_counts to configure GPU media pipeline on Gen8/Gen9Zhao Yakui6-16/+46
If it is not supported, it will fall back to the original config. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Reviewed-by: Charles Daniel <daniel.charles@intel.com>
2016-11-21Query the kernel API to check the EU counts of GPU deviceZhao Yakui2-0/+13
This info can be used to configure the max EU threads of GPU device. >eu_total * 6 V2->V3: Refresh the patches again. V1->V2: Remove the extra bit_field of has_eu_flag. Instead the eu_total > 0 can be used. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Reviewed-by: Charles Daniel <daniel.charles@intel.com>
2016-11-18Add a new gpe function gen8_gpe_pipe_control() for GEN8Xiang, Haihao3-0/+98
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2016-11-18Add a new gpe function gen8_gpe_mi_conditional_batch_buffer_end() for GEN8Xiang, Haihao2-0/+21
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2016-11-18Add a new gpe function gen8_gpe_context_add_surface() to set surface state ↵Xiang, Haihao2-0/+222
on GEN8 v2: Add support for override_offset, clean up the code for 2D surface. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2016-11-18Add a new gpe function gen8_gpe_reset_binding_table() to reset binging tableXiang, Haihao2-0/+19
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2016-11-18Rename gen9_gpe_mi_store_register_mem() to gen8_gpe_mi_store_register_mem()Xiang, Haihao4-12/+12
This function can be used on GEN8 too v2: rebased v3: Fix commit log Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2016-11-18Rename gen9_gpe_mi_flush_dw() to gen8_gpe_mi_flush_dw()Xiang, Haihao4-9/+9
This function can be used on GEN8 too Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2016-11-18Rename gen9_gpe_mi_store_data_imm() to gen8_gpe_mi_store_data_imm()Xiang, Haihao4-6/+6
This function can be used on GEN8 too Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2016-11-18Rename gen9_gpe_mi_batch_buffer_start() to gen8_gpe_mi_batch_buffer_start()Xiang, Haihao4-6/+6
This function can be used on GEN8 too Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2016-11-18Rename gen9_gpe_media_object_walker() to gen8_gpe_media_object_walker()Xiang, Haihao4-4/+4
This function can be used on GEN8 too Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2016-11-18Rename i965_gpe_dri_object_to_2d_gpe_resource() to ↵Xiang, Haihao4-12/+12
i965_dri_object_to_2d_gpe_resource() Like as i965_dri_object_to_buffer_gpe_resource(), use i965_ instead of i965_gpe_ as prefix Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2016-11-18Rename gen8p_gpe_context_map_curbe()/gen8p_gpe_context_unmap_curbe() to ↵Xiang, Haihao4-16/+16
i965_gpe_context_map_curbe()/i965_gpe_context_unmap_curbe() gpe_context->curbe.bo always points to the curbe buffer now, and the two functions can be used on all platforms Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2016-11-18Fix curbe length in CMD_MEDIA_CURBE_LOAD on GEN8+Xiang, Haihao1-1/+1
It is multiple of 64 bytes Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2016-11-18Fix the size calculation of the required memory for dynamic state bufferXiang, Haihao1-4/+5
Make sure the size for each part in dynamic state buffer is multiple of 64 bytes. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2016-11-18Move sampler state related settings to the inner structure in i965_gpe_contextXiang, Haihao7-26/+45
User can set sampler entry size and the number of sampler entries now. sampler.bo is always set even if the sampler state is a part of the dynamic state buffer, hence we can use the corresponding settings no matter sampler state is a part of the dynamic state buffer or not. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2016-11-18Move interface descriptor remapping table related settings to the inner ↵Xiang, Haihao8-27/+40
structure in i965_gpe_context This patch delete idrt_size and use (idrt.max_entries * idrt.entry_size) instead. idrt.bo is always set even if the interface descriptor remapping table is a part of the dynamic state buffer, hence we can use the corresponding settings no matter this table is a part of the dynamic state buffer or not. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
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