diff options
| author | Xiang, Haihao <haihao.xiang@intel.com> | 2016-11-10 22:13:44 +0800 |
|---|---|---|
| committer | Xiang, Haihao <haihao.xiang@intel.com> | 2016-11-18 16:31:44 +0800 |
| commit | 876855e69ad94595957eb9ed30af0f2c38a33fc0 (patch) | |
| tree | e58b6d5c94331366e670d740ab2b6e046af9b296 | |
| parent | aad41b8370ee43f5a0f0d39f01fd6bcef6e9a259 (diff) | |
Add a new gpe function gen8_gpe_mi_conditional_batch_buffer_end() for GEN8
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
| -rw-r--r-- | src/i965_gpe_utils.c | 16 | ||||
| -rw-r--r-- | src/i965_gpe_utils.h | 5 |
2 files changed, 21 insertions, 0 deletions
diff --git a/src/i965_gpe_utils.c b/src/i965_gpe_utils.c index eed0366..f26d738 100644 --- a/src/i965_gpe_utils.c +++ b/src/i965_gpe_utils.c @@ -2424,3 +2424,19 @@ gen8_gpe_context_add_surface(struct i965_gpe_context *gpe_context, dri_bo_unmap(gpe_context->surface_state_binding_table.bo); } + +void +gen8_gpe_mi_conditional_batch_buffer_end(VADriverContextP ctx, + struct intel_batchbuffer *batch, + struct gpe_mi_conditional_batch_buffer_end_parameter *param) +{ + __OUT_BATCH(batch, (MI_CONDITIONAL_BATCH_BUFFER_END | + (1 << 21) | + (4 - 2))); /* Always use PPGTT */ + __OUT_BATCH(batch, param->compare_data); + __OUT_RELOC64(batch, + param->bo, + I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0, + param->offset); + +} diff --git a/src/i965_gpe_utils.h b/src/i965_gpe_utils.h index 7a5db34..debc1f9 100644 --- a/src/i965_gpe_utils.h +++ b/src/i965_gpe_utils.h @@ -532,4 +532,9 @@ gen8_gpe_context_add_surface(struct i965_gpe_context *gpe_context, struct i965_gpe_surface *gpe_surface, int index); +extern void +gen8_gpe_mi_conditional_batch_buffer_end(VADriverContextP ctx, + struct intel_batchbuffer *batch, + struct gpe_mi_conditional_batch_buffer_end_parameter *param); + #endif /* _I965_GPE_UTILS_H_ */ |