diff options
| author | Xiang, Haihao <haihao.xiang@intel.com> | 2016-12-24 00:01:52 +0800 |
|---|---|---|
| committer | Xiang, Haihao <haihao.xiang@intel.com> | 2016-12-28 16:23:32 +0800 |
| commit | 8598c0b0c2be4063647ce220057773db79c6a778 (patch) | |
| tree | 6d72d327cd6b0eae8f502b66c1dc1bb81768c829 | |
| parent | 23d0c8725e9f2ffd0665c5186049f149b996a488 (diff) | |
VDEnc: update the value of inter rounding for CQP mode
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Kelley, Sean V <sean.v.kelley@intel.com>
| -rw-r--r-- | src/gen9_vdenc.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/gen9_vdenc.c b/src/gen9_vdenc.c index de6f510..a1a86d1 100644 --- a/src/gen9_vdenc.c +++ b/src/gen9_vdenc.c @@ -3012,6 +3012,10 @@ gen9_vdenc_mfx_avc_slice_state(VADriverContextP ctx, int num_ref_l0 = 0, num_ref_l1 = 0; int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type); int slice_qp = pic_param->pic_init_qp + slice_param->slice_qp_delta; // TODO: fix for CBR&VBR */ + int inter_rounding = 0; + + if (vdenc_context->internal_rate_mode != I965_BRC_CQP) + inter_rounding = 3; slice_hor_pos = slice_param->macroblock_address % vdenc_context->frame_width_in_mbs; slice_ver_pos = slice_param->macroblock_address / vdenc_context->frame_height_in_mbs; @@ -3110,7 +3114,7 @@ gen9_vdenc_mfx_avc_slice_state(VADriverContextP ctx, (grow << 0)); OUT_BCS_BATCH(batch, (1 << 31) | - (3 << 28) | + (inter_rounding << 28) | (1 << 27) | (5 << 24) | (correct[5] << 20) | |