Rename gen9_gpe_mi_flush_dw() to gen8_gpe_mi_flush_dw()

This function can be used on GEN8 too

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>

4 files changed, 9 insertions, 9 deletions

diff --git a/src/gen9_vdenc.c b/src/gen9_vdenc.c
index 8cddc41..35373f3 100644
--- a/src/gen9_vdenc.c
+++ b/src/gen9_vdenc.c
@@ -1875,7 +1875,7 @@ gen9_vdenc_huc_brc_init_reset(VADriverContextP ctx,
 
     memset(&mi_flush_dw_params, 0, sizeof(mi_flush_dw_params));
     mi_flush_dw_params.video_pipeline_cache_invalidate = 1;
-    gen9_gpe_mi_flush_dw(ctx, batch, &mi_flush_dw_params);
+    gen8_gpe_mi_flush_dw(ctx, batch, &mi_flush_dw_params);
 }
 
 static void
@@ -2287,7 +2287,7 @@ gen9_vdenc_huc_brc_update(VADriverContextP ctx,
 
     memset(&mi_flush_dw_params, 0, sizeof(mi_flush_dw_params));
     mi_flush_dw_params.video_pipeline_cache_invalidate = 1;
-    gen9_gpe_mi_flush_dw(ctx, batch, &mi_flush_dw_params);
+    gen8_gpe_mi_flush_dw(ctx, batch, &mi_flush_dw_params);
 
     if (!vdenc_context->brc_initted || vdenc_context->brc_need_reset) {
         struct gpe_mi_conditional_batch_buffer_end_parameter mi_conditional_batch_buffer_end_params;
@@ -2350,7 +2350,7 @@ gen9_vdenc_huc_brc_update(VADriverContextP ctx,
 
     memset(&mi_flush_dw_params, 0, sizeof(mi_flush_dw_params));
     mi_flush_dw_params.video_pipeline_cache_invalidate = 1;
-    gen9_gpe_mi_flush_dw(ctx, batch, &mi_flush_dw_params);
+    gen8_gpe_mi_flush_dw(ctx, batch, &mi_flush_dw_params);
 
     /* Store HUC_STATUS */
     memset(&mi_store_register_mem_params, 0, sizeof(mi_store_register_mem_params));
@@ -3407,7 +3407,7 @@ gen9_vdenc_mfx_vdenc_avc_slices(VADriverContextP ctx,
 
     memset(&mi_flush_dw_params, 0, sizeof(mi_flush_dw_params));
     mi_flush_dw_params.video_pipeline_cache_invalidate = 1;
-    gen9_gpe_mi_flush_dw(ctx, batch, &mi_flush_dw_params);
+    gen8_gpe_mi_flush_dw(ctx, batch, &mi_flush_dw_params);
 }
 
 static void
@@ -3502,7 +3502,7 @@ gen9_vdenc_read_status(VADriverContextP ctx, struct intel_encoder_context *encod
     int i;
 
     memset(&mi_flush_dw_params, 0, sizeof(mi_flush_dw_params));
-    gen9_gpe_mi_flush_dw(ctx, batch, &mi_flush_dw_params);
+    gen8_gpe_mi_flush_dw(ctx, batch, &mi_flush_dw_params);
 
     memset(&mi_store_register_mem_params, 0, sizeof(mi_store_register_mem_params));
     mi_store_register_mem_params.mmio_offset = MFC_BITSTREAM_BYTECOUNT_FRAME_REG; /* TODO: fix it if VDBOX2 is used */
diff --git a/src/gen9_vp9_encoder.c b/src/gen9_vp9_encoder.c
index 4b80716..98ae3ca 100644
--- a/src/gen9_vp9_encoder.c
+++ b/src/gen9_vp9_encoder.c
@@ -5673,7 +5673,7 @@ gen9_vp9_read_mfc_status(VADriverContextP ctx, struct intel_encoder_context *enc
     status_buffer = &(vp9_state->status_buffer);
 
     memset(&mi_flush_dw_param, 0, sizeof(mi_flush_dw_param));
-    gen9_gpe_mi_flush_dw(ctx, batch, &mi_flush_dw_param);
+    gen8_gpe_mi_flush_dw(ctx, batch, &mi_flush_dw_param);
 
     memset(&mi_store_reg_mem_param, 0, sizeof(mi_store_reg_mem_param));
     mi_store_reg_mem_param.bo = status_buffer->bo;
@@ -5705,7 +5705,7 @@ gen9_vp9_read_mfc_status(VADriverContextP ctx, struct intel_encoder_context *enc
                                status_buffer->vp9_image_ctrl_reg_offset;
     gen9_gpe_mi_store_register_mem(ctx, batch, &mi_store_reg_mem_param);
 
-    gen9_gpe_mi_flush_dw(ctx, batch, &mi_flush_dw_param);
+    gen8_gpe_mi_flush_dw(ctx, batch, &mi_flush_dw_param);
 
     return;
 }
diff --git a/src/i965_gpe_utils.c b/src/i965_gpe_utils.c
index 85cdd50..2f328f9 100644
--- a/src/i965_gpe_utils.c
+++ b/src/i965_gpe_utils.c
@@ -1479,7 +1479,7 @@ i965_unmap_gpe_resource(struct i965_gpe_resource *res)
 }
 
 void
-gen9_gpe_mi_flush_dw(VADriverContextP ctx,
+gen8_gpe_mi_flush_dw(VADriverContextP ctx,
                      struct intel_batchbuffer *batch,
                      struct gpe_mi_flush_dw_parameter *params)
 {
diff --git a/src/i965_gpe_utils.h b/src/i965_gpe_utils.h
index e6cc3dc..517f353 100644
--- a/src/i965_gpe_utils.h
+++ b/src/i965_gpe_utils.h
@@ -362,7 +362,7 @@ void *i965_map_gpe_resource(struct i965_gpe_resource *res);
 
 void i965_unmap_gpe_resource(struct i965_gpe_resource *res);
 
-void gen9_gpe_mi_flush_dw(VADriverContextP ctx,
+void gen8_gpe_mi_flush_dw(VADriverContextP ctx,
                           struct intel_batchbuffer *batch,
                           struct gpe_mi_flush_dw_parameter *params);