summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)AuthorFilesLines
2023-02-13arm64: defconfig: enable drivers required by the Qualcomm SA8775P platformBartosz Golaszewski1-0/+2
Enable the pinctrl, GCC clock and interconnect drivers in order to allow booting SA8775P boards. The drivers need to be built-in for QUPv3 and subsequently UART console to work. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Eric Chanudet <echanude@redhat.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230209103531.469809-1-brgl@bgdev.pl
2023-02-13arm64: dts: qcom: sm8550: remove invalid interconnect property from cryptobamNeil Armstrong1-2/+0
The interconnect property is already present in the qce node, which is the consumer of the cryptobam, so no need for an interconnect property as documented by the bindings. Fixes: 433477c3bf0b ("arm64: dts: qcom: sm8550: add QCrypto nodes") Suggested-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230209-topic-sm8550-upstream-cryptobam-remove-interconnect-v1-1-84587c7bad0f@linaro.org
2023-02-13arm64: dts: qcom: sc7280: Adjust zombie PWM frequencyOwen Yang1-2/+2
Tune the PWM to solve screen flashing issue and high frequency noise. While at it, the comment for the PWM settings incorrectly said we were using a 5kHz duty cycle. It should have said "period", not "duty cycle". Correct this while updating the values. Signed-off-by: Owen Yang <ecs.taipeikernel@gmail.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230213105803.v2.1.I610cef0ead2d5df1f7bd18bc0e0ae040b03725d0@changeid
2023-02-13arm64: dts: qcom: sc8280xp-pmics: Specify interrupt parent explicitlyManivannan Sadhasivam1-6/+6
Nodes like pwrkey, resin, iadc, adc-tm, temp-alarm which are the grand children of spmi_bus node represent the interrupt generating devices but don't have "interrupt-parent" property. As per the devicetree spec v0.3, section 2.4: "The physical wiring of an interrupt source to an interrupt controller is represented in the devicetree with the interrupt-parent property. Nodes that represent interrupt-generating devices contain an interrupt-parent property which has a phandle value that points to the device to which the device’s interrupts are routed, typically an interrupt controller. If an interrupt-generating device does not have an interrupt-parent property, its interrupt parent is assumed to be its devicetree parent." This clearly says that if the "interrupt-parent" property is absent, then the immediate devicetree parent will be assumed as the interrupt parent. But the immediate parents of these nodes are not interrupt controllers themselves. This may lead to failure while wiring the interrupt for these nodes by an operating system. But a few operating systems like Linux, workaround this issue by walking up the parent nodes until it finds the "interrupt-cells" property. Then the node that has the "interrupt-cells" property will be used as the interrupt parent. But this workaround is not as per the DT spec and is not being implemented by other operating systems such as OpenBSD. Hence, fix this issue by adding the "interrupts-extended" property that explicitly specifies the spmi_bus node as the interrupt parent. Note that the "interrupts-extended" property is chosen over "interrupt-parent" as it allows specifying both interrupt parent phandle and interrupt specifiers in a single property. Reported-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230213090118.11527-1-manivannan.sadhasivam@linaro.org
2023-02-13arm64: dts: qcom: sm7225-fairphone-fp4: enable remaining i2c bussesLuca Weiss1-0/+33
Enable all i2c busses where something is connected on this phone. Add comments as placeholders for which components are still missing. Also enable gpi_dma and the other qupv3 for that. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230213-fp4-more-i2c-v2-2-1c459c572f80@fairphone.com
2023-02-13arm64: dts: qcom: sm7225-fairphone-fp4: move status property downLuca Weiss1-17/+17
Currently the dts contains a mix of status-as-first-property (old qcom style) and status-as-last-property (new style). Move all status properties down to the bottom once and for all so that the style is consistent between different nodes. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230213-fp4-more-i2c-v2-1-1c459c572f80@fairphone.com
2023-02-13arm64: dts: qcom: pmk8350: Use the correct PON compatibleKonrad Dybcio1-1/+1
A special compatible was introduced for PMK8350 both in the driver and the bindings to facilitate for 2 base registers (PBS & HLOS). Use it. Fixes: b2de43136058 ("arm64: dts: qcom: pmk8350: Add peripherals for pmk8350") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230213212930.2115182-1-konrad.dybcio@linaro.org
2023-02-13arm64: defconfig: Enable DisplayPort on SC8280XP laptopsBjorn Andersson1-0/+2
The QCOM_PMIC_GLINK implements the parts of a TCPM necessary for negotiating DP altmode and the TYPEC_MUX_GPIO_SBU driver is used for controlling connection and orientation switching of the SBU lanes in the USB-C connector Enable these to enable USB Type-C DisplayPort on SC8280XP laptops. Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230213215619.1362566-5-quic_bjorande@quicinc.com
2023-02-13arm64: dts: qcom: sc8280xp-x13s: Enable external displayBjorn Andersson1-2/+178
Like on the CRD, add the necessary nodes to enable USB Type-C altmode-based external display on the Lenovo ThinkPad X13s. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230213215619.1362566-4-quic_bjorande@quicinc.com
2023-02-13arm64: dts: qcom: sc8280xp-crd: Introduce pmic_glinkBjorn Andersson2-2/+211
The SC8280XP CRD control over battery management and its two USB Type-C port using pmic_glink and two GPIO-based SBU muxes. Enable the two DisplayPort instances, GPIO SBU mux instance and pmic_glink with the two connectors on the CRD. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230213215619.1362566-3-quic_bjorande@quicinc.com
2023-02-13arm64: dts: qcom: sc8280xp: Add USB-C-related DP blocksBjorn Andersson1-4/+168
Add the two DisplayPort controllers that are attached to QMP phys for providing display output on USB Type-C. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230213215619.1362566-2-quic_bjorande@quicinc.com
2023-02-13arm64: dts: qcom: sm8350-hdk: enable GPUDmitry Baryshkov1-0/+8
Enable the GPU on the SM8350-HDK device. The ZAP shader is required for the GPU to function properly. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230209133839.762631-7-dmitry.baryshkov@linaro.org
2023-02-13arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodesDmitry Baryshkov1-0/+178
Add device nodes required to enable GPU on the SM8350 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> [bjorn: Workaround for lacking RPMH_REGULATOR_LEVEL_LOW_SVS_L1 constant] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230209133839.762631-6-dmitry.baryshkov@linaro.org
2023-02-13arm64: dts: qcom: sm8350: finish reordering nodesDmitry Baryshkov1-270/+270
Finish reordering DT nodes by their address. Move PDC, tsens, AOSS, SRAM, SPMI and TLMM nodes to the proper position. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230209133839.762631-5-dmitry.baryshkov@linaro.org
2023-02-13arm64: dts: qcom: sm8350: move more nodes to correct placeDmitry Baryshkov1-157/+157
Continue ordering DT nodes by their address. Move RNG, UFS, system NoC and SLPI nodes to the proper position. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230209133839.762631-4-dmitry.baryshkov@linaro.org
2023-02-13arm64: dts: qcom: sm8350: reorder device nodesDmitry Baryshkov1-375/+375
Somehow sm8350 got its device nodes not fully sorted. Start reordering DT nodes by their address. Move apps SMMU, GIC, timer, apps RSC, cpufreq ADSP and cDSP nodes to the end to the proper position at the end of /soc/. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230209133839.762631-3-dmitry.baryshkov@linaro.org
2023-02-13char/agp: introduce asm-generic/agp.hMike Rapoport10-73/+5
There are several architectures that duplicate definitions of map_page_into_agp(), unmap_page_from_agp() and flush_agp_cache(). Define those in asm-generic/agp.h and use it instead of duplicated per-architecture headers. Signed-off-by: Mike Rapoport (IBM) <rppt@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-02-13char/agp: consolidate {alloc,free}_gatt_pages()Mike Rapoport6-36/+0
There is a copy of alloc_gatt_pages() and free_gatt_pages in several architectures in arch/$ARCH/include/asm/agp.h. All the copies do exactly the same: alias alloc_gatt_pages() to __get_free_pages(GFP_KERNEL) and alias free_gatt_pages() to free_pages(). Define alloc_gatt_pages() and free_gatt_pages() in drivers/char/agp/agp.h and drop per-architecture definitions. Signed-off-by: Mike Rapoport (IBM) <rppt@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-02-13x86/uv: Use irq_domain_create_hierarchy()Johan Hovold1-4/+3
Use the irq_domain_create_hierarchy() helper to create the hierarchical domain, which both serves as documentation and avoids poking at irqdomain internals. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Hsin-Yi Wang <hsinyi@chromium.org> Tested-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20230213104302.17307-14-johan+linaro@kernel.org
2023-02-13x86/ioapic: Use irq_domain_create_hierarchy()Johan Hovold1-5/+2
Use the irq_domain_create_hierarchy() helper to create the hierarchical domain, which both serves as documentation and avoids poking at irqdomain internals. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Hsin-Yi Wang <hsinyi@chromium.org> Tested-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20230213104302.17307-13-johan+linaro@kernel.org
2023-02-13arm64: configs: Add virtconfigMark Brown2-0/+45
Provide a slimline configuration intended to be booted on virtual machines, with the goal of providing a light configuration which will boot on and enable features available in mach-virt. This is defined in terms of the standard defconfig, with an additional virt.config fragment which disables options unneeded in a virtual configuration. As a first step we just disable all the ARCH_ configuration options, disabling the build of all the SoC specific drivers. This results in a kernel that builds about 25% faster in my testing, if this approach works for people we can add further options. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20230203-arm64-defconfigs-v1-3-cd0694a05f13@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-02-13Merge tag 'clocksource.2023.02.06b' of ↵Thomas Gleixner3-5/+53
git://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu into timers/core Pull clocksource watchdog changes from Paul McKenney: o Improvements to clocksource-watchdog console messages. o Loosening of the clocksource-watchdog skew criteria to match those of NTP (500 parts per million, relaxed from 400 parts per million). If it is good enough for NTP, it is good enough for the clocksource watchdog. o Suspend clocksource-watchdog checking temporarily when high memory latencies are detected. This avoids the false-positive clock-skew events that have been seen on production systems running memory-intensive workloads. o On systems where the TSC is deemed trustworthy, use it as the watchdog timesource, but only when specifically requested using the tsc=watchdog kernel boot parameter. This permits clock-skew events to be detected, but avoids forcing workloads to use the slow HPET and ACPI PM timers. These last two timers are slow enough to cause systems to be needlessly marked bad on the one hand, and real skew does sometimes happen on production systems running production workloads on the other. And sometimes it is the fault of the TSC, or at least of the firmware that told the kernel to program the TSC with the wrong frequency. o Add a tsc=revalidate kernel boot parameter to allow the kernel to diagnose cases where the TSC hardware works fine, but was told by firmware to tick at the wrong frequency. Such cases are rare, but they really have happened on production systems. Link: https://lore.kernel.org/r/20230210193640.GA3325193@paulmck-ThinkPad-P17-Gen-1
2023-02-13MIPS: loongson32: Drop obsolete cpufreq platform deviceKeguang Zhang4-36/+0
The obsolete cpufreq driver was removed, drop the platform device and data accordingly. Link: https://lore.kernel.org/all/20230112135342.3927338-1-keguang.zhang@gmail.com Signed-off-by: Keguang Zhang <keguang.zhang@gmail.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-02-13Merge tag 'qcom-arm64-defconfig-for-6.3-2' of ↵Arnd Bergmann1-0/+21
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/defconfig More ARM64 defconfig updates for v6.3 Here are two more defconfig updates for 6.3, enabling the SM8450 Display clock controller driver, as well as the SDAM driver, a driver exposing SRAM on newer Qualcomm PMICs to other devices. * tag 'qcom-arm64-defconfig-for-6.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: arm64: defconfig: enable Qualcomm SDAM nvmem driver arm64: defconfig: enable SM8450 DISPCC clock driver arm64: defconfig: enable the clock driver for Qualcomm SA8775P platforms arm64: defconfig: enable Visionox VTDR6130 DSI Panel driver arm64: defconfig: enable SM8550 DISPCC clock driver arm64: defconfig: enable Qualcomm PCIe modem drivers arm64: defconfig: Enable SC8280XP Display Clock Controller arm64: defconfig: Enable GCC, TCSRCC, pinctrl and interconnect for SM8550 arm64: defconfig: enable crypto userspace API arm64: defconfig: build SDM_LPASSCC_845 as a module arm64: defconfig: enable camera on Thundercomm RB5 platform arm64: defconfig: build PINCTRL_SM8250_LPASS_LPI as module arm64: defconfig: Enable Qualcomm EUD Link: https://lore.kernel.org/r/20230210181516.2021902-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-02-13Merge tag 'qcom-arm64-for-6.3-2' of ↵Arnd Bergmann70-461/+4361
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt More Qualcomm ARM64 DT updates for 6.3 The new Qualcomm QDU1000 and QRU1000 platforms, and the IDP device on these are introduced. New support for a couple of USB modem sticks from THWC are introduced, so is support for Xiaomi Mi Pad 5 Pro and the Pro SKU of the Herobrine device. The Core Bus Fabric (CBF) is introduced on MSM8996. Interconnect paths for UFS are also described. A few fixes related to the power-grid of herobrine, on SC7280, are introduced. QFPROM is introduced on IPQ8074 and Interconnect providers are added for SDM670. On SDM845 the duplicated wcd9340 audio coded description is moved from devices to a common file, audio devices are added to the OnePlus 6 and 6T. On SM6115 debug UART, SMP2P, watchdog nodes are introduced, and the platform is switched to use #address/size-cells of 2, in line with most other platforms. Camera control interface and clock controllers are added for SM6350, and the CCI interface is enabled on the Fairphone FP4. On SM8350 the interconnect reference of SDHCI controller is corrected, DSI1 PHY clocks are properly described as sources for the Display clock controller and DSI1 is wired up to the display controller. The firmware paths are corrected for the Sony Xperia Nagara platform. The GPR bus, audio servic3es and LPASS pinctrl nodes are added for the SM8550 platform. Additionally a few small typos/errors are corrected. gpio-ranges are corrected across MSM8953, SM6115 and SC8280XP and a range of DT validation issues are corrected. * tag 'qcom-arm64-for-6.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (81 commits) arm64: dts: qcom: sc7280: Power herobrine's 3.3 eDP/TS rail more properly arm64: dts: qcom: pmk8550: fix PON compatible arm64: dts: qcom: sm8550: fix DSI controller compatible arm64: dts: qcom: sc7280: Hook up the touchscreen IO rail on evoker arm64: dts: qcom: sc7280: Hook up the touchscreen IO rail on villager arm64: dts: qcom: sc7280: Add 3ms ramp to herobrine's pp3300_left_in_mlb arm64: dts: qcom: sc7280: On QCard, regulator L3C should be 1.8V arm64: dts: qcom: sc8280xp: correct LPASS GPIO gpio-ranges arm64: dts: qcom: msm8992-lg-bullhead: Enable regulators arm64: dts: qcom: sm6115: correct TLMM gpio-ranges arm64: dts: qcom: msm8953: correct TLMM gpio-ranges arm64: dts: qcom: msm8992-lg-bullhead: Correct memory overlaps with the SMEM and MPSS memory regions arm64: dts: qcom: sm8350-hdk: correct LT9611 pin function arm64: dts: qcom: sm8350-hdk: align pin config node names with bindings arm64: dts: qcom: sm6350: Use specific qmpphy compatible arm64: dts: qcom: sm6115: Add smp2p nodes arm64: dts: qcom: sm7225-fairphone-fp4: Enable CCI busses arm64: dts: qcom: sm6350: Add CCI nodes arm64: dts: qcom: sm6350: Add camera clock controller dt-bindings: clock: add QCOM SM6350 camera clock bindings ... Link: https://lore.kernel.org/r/20230210192908.2039976-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-02-13Merge tag 'qcom-dts-for-6.3-2' of ↵Arnd Bergmann13-41/+216
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt More Qualcomm ARM32 DTS updates for 6.3 This adds backlight, notification LED, vibrator, volume keys and hall sensor to the OnePlus One, and provides a range of Devicetree validation fixes across various platforms. * tag 'qcom-dts-for-6.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (22 commits) ARM: dts: qcom: align OPP table names with DT schema ARM: dts: qcom: msm8974-oneplus-bacon: Add notification LED ARM: dts: qcom: msm8974-oneplus-bacon: Add backlight ARM: dts: qcom: msm8974-oneplus-bacon: Add volume keys and hall sensor ARM: dts: qcom: msm8974-oneplus-bacon: Add vibrator ARM: dts: qcom: pm8941: Add vibrator node ARM: dts: qcom: sdx55: correct TLMM gpio-ranges dt-bindings: arm: qcom: add the sa8775p-ride board ARM: dts: qcom: apq8064: add second DSI host and PHY ARM: dts: qcom: apq8060-dragonboard: align MPP pin node names with DT schema dt-bindings: arm: qcom: Add Xiaomi Mi Pad 5 Pro (xiaomi-elish) ARM: dts: qcom-sdx65: align RPMh regulator nodes with bindings ARM: dts: qcom-sdx55: align RPMh regulator nodes with bindings ARM: dts: qcom: use "okay" for status ARM: dts: qcom: sdx65: Add Qcom SMMU-500 as the fallback for IOMMU node ARM: dts: qcom: sdx55: Add Qcom SMMU-500 as the fallback for IOMMU node ARM: dts: qcom: apq8064: use hdmi_phy for the MMCC's hdmipll clock ARM: dts: qcom: apq8064: add #clock-cells to the HDMI PHY node ARM: dts: qcom: ipq8064: move reg-less nodes outside soc node dt-bindings: qcom: Document msm8916-thwc-uf896 and ufi001c ... Link: https://lore.kernel.org/r/20230210185846.2032601-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-02-13Merge tag 'samsung-dt-6.3-2' of ↵Arnd Bergmann7-29/+24
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Samsung DTS ARM changes for v6.3, part two Several cleanups pointed out by `make dtbs_check`: 1. Align LED status node name with bindings. 2. Drop redundant properties. 3. Move i2c-gpio node out of soc to top-level, as soc node is expected to have only MMIO nodes. 4. Correct SPI NOR flash compatible in SMDK5250 and SMDKv310. 5. Align GPIO property names in WM1811-family codec nodes with bindings. 6. Correct MAX98090 codec DAI cells in Snow. * tag 'samsung-dt-6.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos: correct max98090 DAI argument in Snow ARM: dts: s5pv210: add "gpios" suffix to wlf,ldo1ena on Aries ARM: dts: exynos: add "gpios" suffix to wlf,ldo1ena on Arndale ARM: dts: exynos: add "gpios" suffix to wlf,ldo1ena on Midas ARM: dts: exynos: correct SPI nor compatible in SMDK5250 ARM: dts: exynos: correct SPI nor compatible in SMDKv310 ARM: dts: exynos: move I2C10 out of soc node on Arndale ARM: dts: exynos: drop redundant address/size cells from I2C10 on Arndale ARM: dts: exynos: drop default status from I2C10 on Arndale ARM: dts: exynos: align status led name with bindings on Origen4210 Link: https://lore.kernel.org/r/20230211113103.58894-1-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-02-13clocksource/drivers/riscv: Get rid of clocksource_arch_init() callbackLad Prabhakar2-10/+0
Having a clocksource_arch_init() callback always sets vdso_clock_mode to VDSO_CLOCKMODE_ARCHTIMER if GENERIC_GETTIMEOFDAY is enabled, this is required for the riscv-timer. This works for platforms where just riscv-timer clocksource is present. On platforms where other clock sources are available we want them to register with vdso_clock_mode set to VDSO_CLOCKMODE_NONE. On the Renesas RZ/Five SoC OSTM block can be used as clocksource [0], to avoid multiple clock sources being registered as VDSO_CLOCKMODE_ARCHTIMER move setting of vdso_clock_mode in the riscv-timer driver instead of doing this in clocksource_arch_init() callback as done similarly for ARM/64 architecture. [0] drivers/clocksource/renesas-ostm.c Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Tested-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20221229224601.103851-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2023-02-13RISC-V: time: initialize hrtimer based broadcast clock event deviceConor Dooley1-0/+3
Similarly to commit 022eb8ae8b5e ("ARM: 8938/1: kernel: initialize broadcast hrtimer based clock event device"), RISC-V needs to initiate hrtimer based broadcast clock event device before C3STOP can be used. Otherwise, the introduction of C3STOP for the RISC-V arch timer in commit 232ccac1bd9b ("clocksource/drivers/riscv: Events are stopped during CPU suspend") leaves us without any broadcast timer registered. This prevents the kernel from entering oneshot mode, which breaks timer behaviour, for example clock_nanosleep(). A test app that sleeps each cpu for 6, 5, 4, 3 ms respectively, HZ=250 & C3STOP enabled, the sleep times are rounded up to the next jiffy: == CPU: 1 == == CPU: 2 == == CPU: 3 == == CPU: 4 == Mean: 7.974992 Mean: 7.976534 Mean: 7.962591 Mean: 3.952179 Std Dev: 0.154374 Std Dev: 0.156082 Std Dev: 0.171018 Std Dev: 0.076193 Hi: 9.472000 Hi: 10.495000 Hi: 8.864000 Hi: 4.736000 Lo: 6.087000 Lo: 6.380000 Lo: 4.872000 Lo: 3.403000 Samples: 521 Samples: 521 Samples: 521 Samples: 521 Link: https://lore.kernel.org/linux-riscv/YzYTNQRxLr7Q9JR0@spud/ Fixes: 232ccac1bd9b ("clocksource/drivers/riscv: Events are stopped during CPU suspend") Suggested-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20230103141102.772228-2-apatel@ventanamicro.com Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
2023-02-12Merge tag 'powerpc-6.2-5' of ↵Linus Torvalds3-3/+5
git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull powerpc fixes from Michael Ellerman: - Fix interrupt exit race with security mitigation switching. - Don't select ARCH_WANTS_NO_INSTR until warnings are fixed. - Build fix for CONFIG_NUMA=n. Thanks to Nicholas Piggin, Randy Dunlap, and Sachin Sant. * tag 'powerpc-6.2-5' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: powerpc/64s/interrupt: Fix interrupt exit race with security mitigation switch powerpc/kexec_file: fix implicit decl error powerpc: Don't select ARCH_WANTS_NO_INSTR
2023-02-11Merge tag 'x86-urgent-2023-02-11' of ↵Linus Torvalds2-1/+3
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fixes from Ingo Molnar: "Fix a kprobes bug, plus add a new Intel model number to the upstream <asm/intel-family.h> header for drivers to use" * tag 'x86-urgent-2023-02-11' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/cpu: Add Lunar Lake M x86/kprobes: Fix 1 byte conditional jump target
2023-02-11perf/x86/intel/uncore: Add Meteor Lake supportKan Liang3-0/+169
The uncore subsystem for Meteor Lake is similar to the previous Alder Lake. The main difference is that MTL provides PMU support for different tiles, while ADL only provides PMU support for the whole package. On ADL, there are CBOX, ARB, and clockbox uncore PMON units. On MTL, they are split into CBOX/HAC_CBOX, ARB/HAC_ARB, and cncu/sncu which provides a fixed counter for clockticks. Also, new MSR addresses are introduced on MTL. The IMC uncore PMON is the same as Alder Lake. Add new PCIIDs of IMC for Meteor Lake. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20230210190238.1726237-1-kan.liang@linux.intel.com
2023-02-11x86/perf/zhaoxin: Add stepping check for ZXCsilviazhao1-1/+7
Some of Nano series processors will lead GP when accessing PMC fixed counter. Meanwhile, their hardware support for PMC has not announced externally. So exclude Nano CPUs from ZXC by checking stepping information. This is an unambiguous way to differentiate between ZXC and Nano CPUs. Following are Nano and ZXC FMS information: Nano FMS: Family=6, Model=F, Stepping=[0-A][C-D] ZXC FMS: Family=6, Model=F, Stepping=E-F OR Family=6, Model=0x19, Stepping=0-3 Fixes: 3a4ac121c2ca ("x86/perf: Add hardware performance events support for Zhaoxin CPU.") Reported-by: Arjan <8vvbbqzo567a@nospam.xutrox.com> Reported-by: Kevin Brace <kevinbrace@gmx.com> Signed-off-by: silviazhao <silviazhao-oc@zhaoxin.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://bugzilla.kernel.org/show_bug.cgi?id=212389
2023-02-11perf/x86/intel/ds: Fix the conversion from TSC to perf timeKan Liang1-9/+26
The time order is incorrect when the TSC in a PEBS record is used. $perf record -e cycles:upp dd if=/dev/zero of=/dev/null count=10000 $ perf script --show-task-events perf-exec 0 0.000000: PERF_RECORD_COMM: perf-exec:915/915 dd 915 106.479872: PERF_RECORD_COMM exec: dd:915/915 dd 915 106.483270: PERF_RECORD_EXIT(915:915):(914:914) dd 915 106.512429: 1 cycles:upp: ffffffff96c011b7 [unknown] ([unknown]) ... ... The perf time is from sched_clock_cpu(). The current PEBS code unconditionally convert the TSC to native_sched_clock(). There is a shift between the two clocks. If the TSC is stable, the shift is consistent, __sched_clock_offset. If the TSC is unstable, the shift has to be calculated at runtime. This patch doesn't support the conversion when the TSC is unstable. The TSC unstable case is a corner case and very unlikely to happen. If it happens, the TSC in a PEBS record will be dropped and fall back to perf_event_clock(). Fixes: 47a3aeb39e8d ("perf/x86/intel/pebs: Fix PEBS timestamps overwritten") Reported-by: Namhyung Kim <namhyung@kernel.org> Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/all/CAM9d7cgWDVAq8-11RbJ2uGfwkKD6fA-OMwOKDrNUrU_=8MgEjg@mail.gmail.com/
2023-02-11x86/tsc: Do feature check as the very first thingBorislav Petkov (AMD)1-5/+5
Do the feature check as the very first thing in the function. Everything else comes after that and is meaningless work if the TSC CPUID bit is not even set. Switch to cpu_feature_enabled() too, while at it. No functional changes. Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/Y5990CUCuWd5jfBH@zn.tnic
2023-02-11x86/tsc: Make recalibrate_cpu_khz() export GPL onlyBorislav Petkov (AMD)1-2/+1
A quick search doesn't reveal any use outside of the kernel - which would be questionable to begin with anyway - so make the export GPL only. Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/Y599miBzWRAuOwhg@zn.tnic
2023-02-11x86/cacheinfo: Remove unused trace variableBorislav Petkov (AMD)1-4/+1
15cd8812ab2c ("x86: Remove the CPU cache size printk's") removed the last use of the trace local var. Remove it too and the useless trace cache case. No functional changes. Reported-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/20230210234541.9694-1-bp@alien8.de Link: http://lore.kernel.org/r/20220705073349.1512-1-jiapeng.chong@linux.alibaba.com
2023-02-10Merge tag 'soc-fixes-6.2-4' of ↵Linus Torvalds13-20/+37
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC fixes from Arnd Bergmann: "All the changes this time are minor devicetree corrections, the majority being for 64-bit Rockchip SoC support. These are a couple of corrections for properties that are in violation of the binding, some that put the machine into safer operating points for the eMMC and thermal settings, and missing properties that prevented rk356x PCIe and ethernet from working correctly. The changes for amlogic and mediatek address incorrect properties that were preventing the display support on MT8195 and the MMC support on various Meson SoCs from working correctly. The stihxxx-b2120 change fixes the GPIO polarity for the DVB tuner to allow this to be used correctly after a futre driver change, though it has no effect on older kernels" * tag 'soc-fixes-6.2-4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: arm64: dts: meson-gx: Make mmc host controller interrupts level-sensitive arm64: dts: meson-g12-common: Make mmc host controller interrupts level-sensitive arm64: dts: meson-axg: Make mmc host controller interrupts level-sensitive ARM: dts: stihxxx-b2120: fix polarity of reset line of tsin0 port arm64: dts: mediatek: mt8195: Fix vdosys* compatible strings arm64: dts: rockchip: align rk3399 DMC OPP table with bindings arm64: dts: rockchip: set sdmmc0 speed to sd-uhs-sdr50 on rock-3a arm64: dts: rockchip: fix probe of analog sound card on rock-3a arm64: dts: rockchip: add missing #interrupt-cells to rk356x pcie2x1 arm64: dts: rockchip: fix input enable pinconf on rk3399 ARM: dts: rockchip: add power-domains property to dp node on rk3288 arm64: dts: rockchip: add io domain setting to rk3566-box-demo arm64: dts: rockchip: remove unsupported property from sdmmc2 for rock-3a arm64: dts: rockchip: drop unused LED mode property from rk3328-roc-cc arm64: dts: rockchip: reduce thermal limits on rk3399-pinephone-pro arm64: dts: rockchip: use correct reset names for rk3399 crypto nodes
2023-02-10Merge tag 'riscv-for-linus-6.2-rc8' of ↵Linus Torvalds5-5/+34
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V fixes from Palmer Dabbelt: "This is a little bigger that I'd hope for this late in the cycle, but they're all pretty concrete fixes and the only one that's bigger than a few lines is pmdp_collapse_flush() (which is almost all boilerplate/comment). It's also all bug fixes for issues that have been around for a while. So I think it's not all that scary, just bad timing. - avoid partial TLB fences for huge pages, which are disallowed by the ISA - avoid missing a frame when dumping stacks - avoid misaligned accesses (and possibly overflows) in kprobes - fix a race condition in tracking page dirtiness" * tag 'riscv-for-linus-6.2-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: Fixup race condition on PG_dcache_clean in flush_icache_pte riscv: kprobe: Fixup misaligned load text riscv: stacktrace: Fix missing the first frame riscv: mm: Implement pmdp_collapse_flush for THP
2023-02-10ARM: reorder defconfig filesArnd Bergmann15-65/+65
Some Kconfig options have moved around, so adapt the defconfig files accordingly. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-02-10arm64: reorder defconfigArnd Bergmann1-28/+28
Some Kconfig options has moved around after a 'make savedefconfig' run, so move them to their new location to make it easier to see what other options got removed. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-02-10KVM: x86: Mitigate the cross-thread return address predictions bugTom Lendacky1-11/+32
By default, KVM/SVM will intercept attempts by the guest to transition out of C0. However, the KVM_CAP_X86_DISABLE_EXITS capability can be used by a VMM to change this behavior. To mitigate the cross-thread return address predictions bug (X86_BUG_SMT_RSB), a VMM must not be allowed to override the default behavior to intercept C0 transitions. Use a module parameter to control the mitigation on processors that are vulnerable to X86_BUG_SMT_RSB. If the processor is vulnerable to the X86_BUG_SMT_RSB bug and the module parameter is set to mitigate the bug, KVM will not allow the disabling of the HLT, MWAIT and CSTATE exits. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Message-Id: <4019348b5e07148eb4d593380a5f6713b93c9a16.1675956146.git.thomas.lendacky@amd.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-02-10x86/speculation: Identify processors vulnerable to SMT RSB predictionsTom Lendacky2-2/+8
Certain AMD processors are vulnerable to a cross-thread return address predictions bug. When running in SMT mode and one of the sibling threads transitions out of C0 state, the other sibling thread could use return target predictions from the sibling thread that transitioned out of C0. The Spectre v2 mitigations cover the Linux kernel, as it fills the RSB when context switching to the idle thread. However, KVM allows a VMM to prevent exiting guest mode when transitioning out of C0. A guest could act maliciously in this situation, so create a new x86 BUG that can be used to detect if the processor is vulnerable. Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Message-Id: <91cec885656ca1fcd4f0185ce403a53dd9edecb7.1675956146.git.thomas.lendacky@amd.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-02-10Merge tag 'amlogic-fixes-v6.2-rc-take2' of ↵Arnd Bergmann3-8/+8
https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into arm/fixes Amlogic fixes for v6.2-rc, take2: - Change MMC controllers interrupts flag to level on all families, fixes irq loss & performance issues when cpu loaded * tag 'amlogic-fixes-v6.2-rc-take2' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux: arm64: dts: meson-gx: Make mmc host controller interrupts level-sensitive arm64: dts: meson-g12-common: Make mmc host controller interrupts level-sensitive arm64: dts: meson-axg: Make mmc host controller interrupts level-sensitive Link: https://lore.kernel.org/r/761c2ebc-7c93-8504-35ae-3e84ad216bcf@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-02-10arm64: dts: meson-gx: Make mmc host controller interrupts level-sensitiveHeiner Kallweit1-3/+3
The usage of edge-triggered interrupts lead to lost interrupts under load, see [0]. This was confirmed to be fixed by using level-triggered interrupts. The report was about SDIO. However, as the host controller is the same for SD and MMC, apply the change to all mmc controller instances. [0] https://www.spinics.net/lists/linux-mmc/msg73991.html Fixes: ef8d2ffedf18 ("ARM64: dts: meson-gxbb: add MMC support") Cc: stable@vger.kernel.org Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/76e042e0-a610-5ed5-209f-c4d7f879df44@gmail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-02-10arm64: dts: meson-g12-common: Make mmc host controller interrupts ↵Heiner Kallweit1-3/+3
level-sensitive The usage of edge-triggered interrupts lead to lost interrupts under load, see [0]. This was confirmed to be fixed by using level-triggered interrupts. The report was about SDIO. However, as the host controller is the same for SD and MMC, apply the change to all mmc controller instances. [0] https://www.spinics.net/lists/linux-mmc/msg73991.html Fixes: 4759fd87b928 ("arm64: dts: meson: g12a: add mmc nodes") Tested-by: FUKAUMI Naoki <naoki@radxa.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Jerome Brunet <jbrunet@baylibre.com> Cc: stable@vger.kernel.org Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/27d89baa-b8fa-baca-541b-ef17a97cde3c@gmail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-02-10arm64: dts: meson-axg: Make mmc host controller interrupts level-sensitiveHeiner Kallweit1-2/+2
The usage of edge-triggered interrupts lead to lost interrupts under load, see [0]. This was confirmed to be fixed by using level-triggered interrupts. The report was about SDIO. However, as the host controller is the same for SD and MMC, apply the change to all mmc controller instances. [0] https://www.spinics.net/lists/linux-mmc/msg73991.html Fixes: 221cf34bac54 ("ARM64: dts: meson-axg: enable the eMMC controller") Reported-by: Peter Suti <peter.suti@streamunlimited.com> Tested-by: Vyacheslav Bocharov <adeep@lexina.in> Tested-by: Peter Suti <peter.suti@streamunlimited.com> Cc: stable@vger.kernel.org Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/c00655d3-02f8-6f5f-4239-ca2412420cad@gmail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-02-09riscv: Fixup race condition on PG_dcache_clean in flush_icache_pteGuo Ren1-1/+3
In commit 588a513d3425 ("arm64: Fix race condition on PG_dcache_clean in __sync_icache_dcache()"), we found RISC-V has the same issue as the previous arm64. The previous implementation didn't guarantee the correct sequence of operations, which means flush_icache_all() hasn't been called when the PG_dcache_clean was set. That would cause a risk of page synchronization. Fixes: 08f051eda33b ("RISC-V: Flush I$ when making a dirty page executable") Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@kernel.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230127035306.1819561-1-guoren@kernel.org Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-02-09riscv: kprobe: Fixup misaligned load textGuo Ren1-3/+5
The current kprobe would cause a misaligned load for the probe point. This patch fixup it with two half-word loads instead. Fixes: c22b0bcb1dd0 ("riscv: Add kprobes supported") Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@kernel.org> Link: https://lore.kernel.org/linux-riscv/878rhig9zj.fsf@all.your.base.are.belong.to.us/ Reported-by: Bjorn Topel <bjorn.topel@gmail.com> Reviewed-by: Björn Töpel <bjorn@kernel.org> Link: https://lore.kernel.org/r/20230204063531.740220-1-guoren@kernel.org Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-02-09Merge tag 'at91-dt-6.3-2' of ↵Arnd Bergmann4-40/+1136
https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dt AT91 device tree updates for 6.3 #2 It contains: - cleanups arround flexcom nodes on SAM9X60 SoC as follows: - preserve same ID for flexcoms and the embedded nodes (e.g. flx4 will embed uart4, spi4, i2c4 but not e.g. uart1, spi2, i2c3); - SoC specific bindings were moved from board specific file to SoC specific file - DMA bindings for all flexcom nodes were added - SoC file was filled with missing flexcom nodes - new SAM9X60 Curiosity board that contains 1 uSDcard interface, 1 SDcard interface, 1 USB device interface, 2 USB Type-A interfaces, 2 CAN interfaces, 1 10/100 Ethernet interface, 1 LCD RGB666 interface, 1 Gb DDR2, 4 Gb NAND Flash, 2Kb EEPROM, leds, button, power regulators, UART and JTAG connectors * tag 'at91-dt-6.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: dts: at91: sam9x60_curiosity: Add device tree for sam9x60 curiosity board dt-bindings: arm: at91: Add info on sam9x60 curiosity ARM: dts: at91: sam9x60: Add missing flexcom definitions ARM: dts: at91: sam9x60: Add DMA bindings for the flexcom nodes ARM: dts: at91: sam9x60: Specify the FIFO size for the Flexcom UART ARM: dts: at91: sam9x60: fix spi4 node ARM: dts: at91: sam9x60: move flexcom definitions ARM: dts: at91: sam9x60: Fix the label numbering for the flexcom functions Link: https://lore.kernel.org/r/20230209084930.289721-1-claudiu.beznea@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-07 01:05:50 +0000