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2014-06-04PCI: tegra: Add Tegra124 supportThierry Reding2-32/+204
The PCIe controller on Tegra124 has two root ports that can be used in a x4/x1 or x2/x1 configuration and can run at PCIe 2.0 link speeds (up to 5 GT/s). The PHY programming has been moved into a separate controller, so the driver now needs to request an external PHY referenced using the device tree. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-04ARM: tegra: Remove legacy PCIe power supply propertiesThierry Reding5-22/+0
These properties are deprecated and no longer of any use. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-04PCI: tegra: Remove deprecated power supply propertiesThierry Reding1-5/+0
These power supply properties are no longer needed since the binding now contains the full set properties to accurately describe the power supply inputs of the Tegra PCIe block. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-04PCI: tegra: Implement accurate power supply schemeThierry Reding1-61/+87
The current description of power supplies doesn't match the hardware. Instead it's designed to support the needs of current designs, which will break as soon as a new design appears that cannot be described using the current assumptions. In order to fully support all possible future designs, all power supply inputs to the PCIe block need to be accurately described and separately configurable. Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Thierry Reding <treding@nvidia.com> --- Changes in v2: - fix typo "enable" -> "disable"
2014-06-04ARM: tegra: Add new PCIe regulator propertiesThierry Reding5-1/+45
These new properties more accurately reflect the real connections of the boards and therefore make it easier to match them up with schematics. Signed-off-by: Thierry Reding <treding@nvidia.com> --- Changes in v2: - reword comment in Cardhu DTS
2014-06-04PCI: tegra: Overhaul regulator usageThierry Reding1-3/+32
The current usage of regulators for the Tegra PCIe block is wrong. It doesn't accurately reflect the actual supply inputs of the IP block and therefore isn't as flexible as it should be. Rectify this by describing all possible supply inputs in the device tree binding documentation and deprecate the old supply properties. Signed-off-by: Thierry Reding <treding@nvidia.com> --- Changes in v2: - fix power rail assignment on Tegra30
2014-06-04PCI: tegra: Make sure the PCIe PLL is really resetThierry Reding1-0/+7
Depending on the prior state of the controller, the PLL reset may not be pulsed. Clear the register bit and set it after a small delay to ensure that the PLL is really reset. Signed-off-by: Eric Yuen <eyuen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-04PCI: tegra: Fix extended configuration space mappingPeter Daifuku1-1/+1
The 16 chunks of 64 KiB that need to be stitched together to make up the configuration space for one bus (1 MiB) are located 24 bits (== 16 MiB) apart in physical address space. This is determined by the start of the extended register field (bits 24-27) in the physical mapping. Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-04PCI: tegra: Clear CLKREQ# enable on port disableThierry Reding1-0/+5
When a root port is disabled, disable the CLKREQ# signal if available. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-04PCI: tegra: Allow building as a moduleThierry Reding1-1/+1
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-04PCI: Export pci_create_root_bus()Thierry Reding1-0/+1
This function is commonly used by PCIe host controller drivers. Export it so that these drivers can be built as modules. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-04PCI: Export MSI helpersThierry Reding1-0/+3
The mask_msi_irq(), unmask_msi_irq() and write_msi_msg() functions are typically used by PCIe host controller drivers. Export them so that these drivers can be built as modules. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-04genirq: Export irq_set_msi_desc()Thierry Reding1-0/+1
The Tegra PCIe host controller driver uses this function. Export it so that the driver can be built as a module. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-04mm, vmalloc: Export get_vm_area()Thierry Reding1-0/+1
The Tegra PCIe host controller driver uses this function. Export it so that the driver can be built as a module. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-04ARM: tegra: Export tegra_cpuidle_pcie_irqs_in_use()Thierry Reding1-0/+1
This function is called by the Tegra PCIe host driver. To allow that driver to be built as a module, export the function. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-04ARM: PCI: Export pci_common_init_dev() and pci_common_exit()Thierry Reding1-0/+2
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-04PCI: tegra: Support driver unbindingThierry Reding1-1/+44
Implement the platform driver's .remove() callback to free all resources allocated during driver setup and call pci_common_exit() to cleanup ARM specific datastructures. Unmap the fixed PCI I/O mapping by calling the new pci_iounmap_io() function in the new .teardown() callback. Finally, no longer set the .suppress_bind_attrs field to true to allow the driver to unbind from a device. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-04ARM: Introduce pci_common_exit()Thierry Reding2-4/+36
In order to support building PCI host drivers as modules, functionality is required to undo the steps performed by pci_common_init(). The PCI core provides much of the functionality already, so add a function that can be called by drivers to wrap the ARM specific bits. This patch does a number of things to achieve this: it adds a .nr field to struct pci_sys_data to keep track of the controller number that was used to initialize it during pci_common_init(). That field is passed to the new .teardown() callback during cleanup to undo what .setup() did. Furthermore the list of pci_sys_data structures setup can optionally be returned via the hw_pci structure's .sys field. If a driver initializes it, then it is assumed to be an empty list that pci_common_init() will append to. Otherwise the old behaviour of keeping a local list only is preserved. If a driver wants to support unloading, then it needs access to this list and pass it to pci_common_exit(). This will iterate over the list, call the new .teardown() callback and remove the root bus associated with each entry. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03ARM: dt: tegra124: add sdhci iommus bindingsHiroshi Doyu1-0/+4
Add sdhci iommus bindings. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03ARM: dt: tegra124: add tegra,smmu entryHiroshi Doyu1-0/+15
Add Tegra SMMU DT entry. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03iommu/tegra124: smmu: add multiple asid_security supportHiroshi Doyu1-6/+32
In Tegra124 the number of MC_SMMU_ASID_SECURITY_# registers increased. Now this info is provided as platfrom data. If no platfrom data the default valude(1) is used. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03iommu/tegra124: smmu: adjust TLB_FLUSH_ASID bit rangeHiroshi Doyu1-3/+6
TLB_FLUSH_ASID bit range depends on the number of asids to support other number than the current 4, especially for a new Tegra124. Based on Terje's internal patch. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Cc: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03iommu/tegra124: smmu: {TLB,PTC} reset value per SoCHiroshi Doyu1-4/+13
T124 has some new register bits in {TLB,PTC}_CONFIG: - TLB_RR_ARB and PTC_REQ_LIMIT - TLB_ACTIVE_LINES 0x20 instead of 0x10 They are defined as platform data now. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03iommu/tegra124: smmu: support more than 32 bit paHiroshi Doyu1-7/+29
Add support for more than 32 bit physical address. If physical address space is 32bit, there will be no register write happening. Based on Pavan's internal patch. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Cc: Pavan Kunapuli <pkunapuli@nvidia.com> Cc: Mark Zhang <markz@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03iommu/tegra124: smmu: add support platform dataHiroshi Doyu2-25/+47
The later Tegra SoC(>= T124) has more registers for MC_SMMU_TRANSLATION_ENABLE_*. Now those info is provided as platfrom data. If those varies a lot on SoCs in the future, we can consider putting them into DT later. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03iommu/tegra124: smmu: convert swgroup ID to asid offsetHiroshi Doyu1-3/+18
Provide a conversion table from swgroup ID to MC_SMMU_<swgroup name>_ASID_0 register offset to support non-linear conversion. This conversion used to be exactly linear but after T124 we need a conversion table to support non-linear cases. We would also need another table to convert swgroup ID to HOTRESET bit. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03iommu/tegra124: smmu: optionaly AHB enables SMMUHiroshi Doyu1-4/+4
SMMU used to depend on AHB bus. AHB driver needs to be populated and AHB_XBAR_CTRL_SMMU_INIT_DONE bit needs to be set earliear than SMMU being populated. Later Tegra SoC (>= T124) doesn't need AHB to enable SMMU on AHB_XBAR_CTRL for AHB_XBAR_CTRL_SMMU_INIT_DONE any more. This setting bit is now optional, depending on DT passing ahb phandle or not. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03iommu/tegra: smmu: add SMMU to an global iommu listHiroshi Doyu1-24/+29
This allows to inquire if SMMU is populated or not. Suggested by Thierry Reding and copied his example code. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03iommu/tegra: smmu: Rename hwgrp -> swgroupsHiroshi Doyu1-18/+18
Use the correct term for SWGROUP related variables and macros. The term "swgroup" is the collection of "memory client". A "memory client" usually represents a HardWare Accelerator(HWA) like GPU. Sometimes a strut device can belong to multiple "swgroup" so that "swgroup's'" is used here. This "swgroups" is the term used in Tegra TRM. Rename along with TRM. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03iommu/tegra: smmu: allow duplicate ASID wirteHiroshi Doyu1-12/+8
The device, which belongs to the same ASID, can try to enable the same ASID as the other swgroup devices. This should be allowed but just skip the actual register write. If the write value is different, it will return -EINVAL. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03iommu/tegra: smmu: get swgroups from DT "iommus="Hiroshi Doyu1-18/+116
This provides the info about which swgroups a device belongs to. This info is passed from DT. This is necessary for the unified SMMU driver among Tegra SoCs since each has different H/W accelerators. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03iommu/tegra: smmu: calculate ASID register offset by IDHiroshi Doyu1-94/+17
ASID register offset is caclulated by SWGROUP ID so that we can get rid of old SoC specific MACROs. This ID conversion is needed for the unified SMMU driver over Tegra SoCs. We use dt-bindings MACRO instead of SoC dependent MACROs. The formula is: MC_SMMU_<swgroup name>_ASID_0 = MC_SMMU_AFI_ASID_0 + ID * 4; Now SWGROUP ID is the global HardWare Accelerator(HWA) identifier among all Tegra SoC except Tegra2. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03iommu/tegra: smmu: register device to iommu dynamicallyHiroshi Doyu2-1/+70
platform_devices are registered as IOMMU'able dynamically via add_device() and remove_device(). Tegra SMMU can have multiple address spaces(AS). IOMMU'able devices can belong to one of them. Multiple IOVA maps are created at boot-up, which can be attached to devices later. We reserve 2 of them for static assignment, AS[0] for system default, AS[1] for AHB clusters as protected domain from others, where there are many traditional pheripheral devices like USB, SD/MMC. They should be isolated from some smart devices like host1x for system robustness. Even if smart devices behaves wrongly, the traditional devices(SD/MMC, USB) wouldn't be affected, and the system could continue most likely. DMA API(ARM) needs ARM_DMA_USE_IOMMU to be enabled. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03ARM: tegra: create a DT header defining SWGROUP IDHiroshi Doyu1-0/+50
Create a header file to define the swgroup IDs used by the IOMMU(SMMU) binding. "swgroup" is a group of H/W clients which a Tegra SoC supports. This unique ID can be used to calculate MC_SMMU_<swgroup name>_ASID_0 register offset and MC_<swgroup name>_HOTRESET_*_0 register bit. This will allow the same header to be used by both device tree files, and drivers implementing this binding, which guarantees that the two stay in sync. This also makes device trees more readable by using names instead of magic numbers. For HOTRESET bit shifting we need another conversion table, which will come later. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Cc: Mark Zhang <markz@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03iommu/core: add ops->{bound,unbind}_driver()Hiroshi Doyu2-2/+15
ops->{bound,unbind}_driver() functions are called at BUS_NOTIFY_{BOUND,UNBIND}_DRIVER respectively. This is necessary to control the device population order. IOMMU master devices depend on an IOMMU device instanciation. IOMMU master devices can be registered to an IOMMU only after it's successfully populated. This IOMMU registration is done via ops->bound_driver(). Currently this population can be deferred if depending IOMMU device hasn't yet been populated in driver core. This cannot be done via ops->add_device() since after add_device() device's population/instanciation can be still deferred via probe(). Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03driver/core: populate devices in order for IOMMUsHiroshi Doyu1-0/+5
IOMMU devices on the bus need to be poplulated first, then iommu master devices are done later. With CONFIG_OF_IOMMU, "iommus=" DT binding would be used to identify whether a device can be an iommu msater or not. If a device can, we'll defer to populate that device till an iommu device is populated. Then, those deferred iommu master devices are populated and configured with help of the already populated iommu device. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03iommu/of: check if dependee iommu is ready or notHiroshi Doyu2-0/+19
IOMMU devices on the bus need to be poplulated first, then iommu master devices are done later. With CONFIG_OF_IOMMU, "iommus=" DT binding would be used to identify whether a device can be an iommu msater or not. If a device can, we'll defer to populate that device till an depending iommu device is populated. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03iommu/of: introduce a global iommu device listHiroshi Doyu2-0/+52
This enables to find an populated IOMMU device via a device node. This can be used to see if an dependee IOMMU is populated or not to keep correct device population order. Client devices need to wait an IOMMU to be populated. Suggested by Thierry Reding and copied his example code. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Cc: Joerg Roedel <joro@8bytes.org> Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03of: introduce of_property_for_each_phandle_with_args()Hiroshi Doyu2-0/+86
Iterating over a property containing a list of phandles with arguments is a common operation for device drivers. This patch adds a new of_property_for_each_phandle_with_args() macro to make the iteration simpler. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Cc: Rob Herring <robherring2@gmail.com> Cc: Grant Likely <grant.likely@linaro.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03HACK: ARM: tegra: Fix interrupt polarity on DalmoreThierry Reding1-1/+1
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03HACK: ARM: tegra: Update DTS for Dalmore A05Thierry Reding1-3/+14
This updates the HDMI related regulators for the Dalmore A05 fab. Note that this should never be merged upstream since it was agreed to only support the Dalmore A04. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03ARM: tegra: cardhu - Enable HDMIThierry Reding3-1/+33
Enable the HDMI output and hotplug detection. Note that HDMI doesn't work on Cardhu for some reason. I remember someone reporting that it worked at some point in time, but that no longer seems to be true. A potential issue might be that EMC clocks are too slow, due to them being set to some safe default, which causes underflow for high HDMI resolutions. This can be made to work by modifying the display A and display B latency allowance registers in the MC. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03ARM: tegra: Add missing clock-names propertiesThierry Reding4-0/+117
clock-names properties are only listed when necessary to differentiate between multiple clocks. The same rule doesn't apply to the reset-names property, though, so add the clock-names property where it's missing for consistency. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03Revert "venice2: remove backlight-boot-off property"Thierry Reding1-0/+2
This reverts commit 44533a1692908ebfb98dc3c462c9535edc42fba1.
2014-06-03Revert "undo cardhu boot off"Thierry Reding1-0/+2
This reverts commit 0af442f0c06b66151a088a481c4dd5d8222471ec.
2014-06-03Revert "undo harmony boot-off"Thierry Reding1-0/+2
This reverts commit ed096432ba42ff8f0e8bd4781a901cf60100ea2d.
2014-06-03Revert "undo dalmore boot-off"Thierry Reding1-0/+2
This reverts commit 286e1ec26da181239ca5eb22f1ef5072160b3ecc.
2014-06-03ARM: tegra: Update default configurationThierry Reding1-0/+4
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03ARM: dt: Fix typo "flaggs" -> "flags"Thierry Reding1-1/+1
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-03enable gk20a clockAlexandre Courbot1-0/+1
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