diff options
| author | Peter Daifuku <pdaifuku@nvidia.com> | 2014-04-04 12:01:31 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2014-06-04 09:30:48 +0200 |
| commit | 248c83e4a110a26c8ab31c332895b21ff9b776cf (patch) | |
| tree | d5e77b79803909e417981e10ee1391c9f7a10c7e | |
| parent | 217eb933bd14e8c2a105e1272a69f4043b67eefc (diff) | |
PCI: tegra: Fix extended configuration space mapping
The 16 chunks of 64 KiB that need to be stitched together to make up the
configuration space for one bus (1 MiB) are located 24 bits (== 16 MiB)
apart in physical address space. This is determined by the start of the
extended register field (bits 24-27) in the physical mapping.
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | drivers/pci/host/pci-tegra.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 83ec6e85a41..86891da477d 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -385,7 +385,7 @@ static struct tegra_pcie_bus *tegra_pcie_bus_alloc(struct tegra_pcie *pcie, for (i = 0; i < 16; i++) { unsigned long virt = (unsigned long)bus->area->addr + i * SZ_64K; - phys_addr_t phys = cs + i * SZ_1M + busnr * SZ_64K; + phys_addr_t phys = cs + i * SZ_16M + busnr * SZ_64K; err = ioremap_page_range(virt, virt + SZ_64K, phys, prot); if (err < 0) { |