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authorHiroshi Doyu <hdoyu@nvidia.com>2014-05-30 14:20:26 +0300
committerThierry Reding <treding@nvidia.com>2014-06-03 17:19:55 +0200
commitbccef9e5aabf6b721bf76a05b921936cf6010c08 (patch)
treee5a82108288eac4f378a59dcab85d8974d97a367
parent174e7d051e880619e0666b5a637af48d15759c60 (diff)
iommu/tegra124: smmu: optionaly AHB enables SMMU
SMMU used to depend on AHB bus. AHB driver needs to be populated and AHB_XBAR_CTRL_SMMU_INIT_DONE bit needs to be set earliear than SMMU being populated. Later Tegra SoC (>= T124) doesn't need AHB to enable SMMU on AHB_XBAR_CTRL for AHB_XBAR_CTRL_SMMU_INIT_DONE any more. This setting bit is now optional, depending on DT passing ahb phandle or not. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--drivers/iommu/tegra-smmu.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c
index 4a326476c36..20dddc305fb 100644
--- a/drivers/iommu/tegra-smmu.c
+++ b/drivers/iommu/tegra-smmu.c
@@ -499,7 +499,10 @@ static int smmu_setup_regs(struct smmu_device *smmu)
smmu_flush_regs(smmu, 1);
- return tegra_ahb_enable_smmu(smmu->ahb);
+ if (smmu->ahb)
+ return tegra_ahb_enable_smmu(smmu->ahb);
+
+ return 0;
}
static void flush_ptc_and_tlb(struct smmu_device *smmu,
@@ -1283,9 +1286,6 @@ static int tegra_smmu_probe(struct platform_device *pdev)
return -EINVAL;
smmu->ahb = of_parse_phandle(dev->of_node, "nvidia,ahb", 0);
- if (!smmu->ahb)
- return -ENODEV;
-
smmu->iommu.dev = dev;
smmu->num_as = asids;
smmu->iovmm_base = base;