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AgeCommit message (Expand)AuthorFilesLines
2016-05-21AMDGPU: Define priorities for register classesMatt Arsenault9-40/+43
2016-05-21AMDGPU: Cleanup lowering actionsMatt Arsenault2-32/+131
2016-05-21AMDGPU: Fix high bits after division optimizationMatt Arsenault6-41/+329
2016-05-21AMDGPU: Fix verifier error when spilling SGPRsMatt Arsenault1-2/+2
2016-05-21AMDGPU: Handle cbranch vccz/vccnzMatt Arsenault3-8/+12
2016-05-21AMDGPU: Implement ReverseBranchConditionMatt Arsenault1-6/+2
2016-05-21AMDGPU: Implement AnalyzeBranchMatt Arsenault9-41/+84
2016-05-20LiveIntervalAnalysis: Rework constructMainRangeFromSubranges()Matthias Braun1-0/+32
2016-05-20MachineVerifier: subregs so not require defs/valnos on every pathMatthias Braun1-0/+26
2016-05-20LiveIntervalAnalysis: Fix missing defs in renameDisconnectedComponents().Matthias Braun1-0/+33
2016-05-18AMDGPU: Fix promote alloca for pointer loadsMatt Arsenault2-3/+43
2016-05-18AMDGPU: Other sizes of popcnt are fastMatt Arsenault1-0/+52
2016-05-18AMDGPU: Fix assert when erroring on a callMatt Arsenault1-3/+15
2016-05-18AMDGPU: Handle alloca promoting with null operandsMatt Arsenault3-0/+91
2016-05-18AMDGPU: Fix a few slightly broken testsMatt Arsenault8-43/+49
2016-05-16AMDGPU/R600: Use correct number of vector elements when lowering private loadsJan Vesely1-0/+105
2016-05-16AMDGPU: Add some private element size testsMatt Arsenault1-6/+126
2016-05-16AMDGPU: Fix promote alloca pass creating huge arraysMatt Arsenault12-52/+233
2016-05-16SelectionDAG: Select min/max when both are usedMatt Arsenault2-1/+86
2016-05-16[llc] New diagnostic handlerRenato Golin5-10/+10
2016-05-14Revert "[llc] New diagnostic handler"Renato Golin5-10/+10
2016-05-14[llc] New diagnostic handlerRenato Golin5-10/+10
2016-05-13AMDGPU/R600: Fold global address operandJan Vesely1-0/+4
2016-05-13AMDGPU/R600: Implement memory loads from constant ASJan Vesely2-71/+19
2016-05-13[AMDGPU] Update nop insertion for debugger usageKonstantin Zhuravlyov1-8/+5
2016-05-13Revert "[llc] New diagnostic handler"Renato Golin5-10/+10
2016-05-13[llc] New diagnostic handlerRenato Golin5-10/+10
2016-05-13AMDGPU: Remove verifier check for scc live insMatt Arsenault1-6/+44
2016-05-12Revert "LiveIntervalAnalysis: Rework constructMainRangeFromSubranges()"Tom Stellard1-32/+0
2016-05-12AMDGPU: Fix breaking IR on instructions with multiple pointer operandsMatt Arsenault3-0/+310
2016-05-11AMDGPU: Split private memory testsJan Vesely3-24/+57
2016-05-11AMDGPU: Change private_element_size to 4Matt Arsenault7-41/+81
2016-05-10liveness.mir requires asserts to use -debug-onlyMatthias Braun1-0/+1
2016-05-10LiveIntervalAnalysis: Rework constructMainRangeFromSubranges()Matthias Braun1-0/+31
2016-05-09[AMDGPU] Clean up debugger testsKonstantin Zhuravlyov3-59/+81
2016-05-09AMDGPU: Fold shift into cvt_f32_ubyteNMatt Arsenault2-2/+122
2016-05-06DetectDeadLanes: Increase precision when detecting undef inputsMatthias Braun2-4/+24
2016-05-06[AMDGPU][llvm-mc] Add support for sendmsg(...) syntax.Artem Tamazov2-5/+5
2016-05-06Revert "AMDGPU/SI: Add amdgpu_kernel calling convention. Part 2."Nikolay Haustov1-61/+0
2016-05-06 AMDGPU/SI: Add amdgpu_kernel calling convention. Part 2.Nikolay Haustov1-0/+61
2016-05-06AMDGPU/SI: Add amdgpu_kernel calling convention. Part 1.Nikolay Haustov1-1/+1
2016-05-05AMDGPU: Run r600 tests lastMatt Arsenault25-48/+47
2016-05-05AMDGPU: Uniform branch conditions can originate with intrinsicsNicolai Haehnle1-0/+27
2016-05-05AMDGPU/SI: Add support for AMD code object version 2.Tom Stellard4-183/+26
2016-05-02AMDGPU: Custom lower v2i32 loads and storesMatt Arsenault1-1/+98
2016-05-02AMDGPU/SI: Use v_readfirstlane_b32 when restoring SGPRs spilled to scratchTom Stellard1-1/+1
2016-05-02AMDGPU: Make i64 loads/stores promote to v2i32Matt Arsenault4-18/+14
2016-05-02AMDGPU/SI: Use the hazard recognizer to break SMEM soft clausesTom Stellard3-39/+37
2016-05-02AMDGPU/SI: Use hazard recognizer to detect DPP hazardsTom Stellard1-2/+6
2016-04-30AMDGPU/SI: Remove wait state handling for SMRD in SIInsertWaitsTom Stellard2-2/+4
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