~vlj/llvm - AMDGPU backend development for LLVM

Age	Commit message (Expand)	Author	Files	Lines
2012-10-19	R600: Remove deprecated code from R600MCCodeEmitterHEAD master	tstellar	1	-129/+9
2012-10-19	R600: Use native operands for KILLGT instruction	tstellar	4	-38/+29
2012-10-19	R600: Use native operands for CUBE, DOT4 instructions	tstellar	3	-68/+46
2012-10-19	R600: Organize pseudo instruction in R600Instructions.td	tstellar	1	-27/+10
2012-10-19	R600: Add support for the AMDGPU::BREAK instruction	tstellar	1	-1/+17
2012-10-19	R600: Lower PRED_X to a native instruction prior to codegen	tstellar	9	-50/+111
2012-10-19	R600: Use native operands for R600_OP3 instructions	tstellar	1	-34/+64
2012-10-19	R600: Use native operands for R600_2OP instructions	tstellar	4	-123/+79
2012-10-19	R600: Use native operands for MOV_IMM_* instructions	tstellar	4	-23/+42
2012-10-19	R600: Use native operands for the MOV Instruction	tstellar	7	-47/+60
2012-10-19	R600: Use native operands for R600_1OP instructions	tstellar	9	-140/+469
2012-10-19	R600: Emit CONTINUE instructions correctly	tstellar	1	-3/+2
2012-10-19	R600: Prevent the CFG Structurizer from emitting extra ENDIFs	tstellar	1	-1/+0
2012-10-19	AMDGPU: Remove unused llvm.AMDGPU.ssg intrinsic	tstellar	2	-8/+0
2012-10-19	R600: Fix DIV_Common pattern use	tstellar	1	-1/+3
2012-10-19	R600: Set FlagOperandIdx for RECIP_IEEE	tstellar	1	-5/+5
2012-10-19	R600: Cayman now uses vector version of EXP_IEEE, LOG_IEEE and RECIPSQRT_CLAMPED	tstellar	1	-9/+19
2012-10-19	R600: Lower fpow(A, B) to fexp(mul(B, flog(A))) at DAG level	tstellar	3	-2/+13
2012-10-16	AMDGPU: Fix build after merge	tstellar	1	-8/+0
2012-10-16	Merge master branch	tstellar	381	-4194/+18653
2012-10-15	R600: use ceil intrinsic instead of llvm.AMDIL.round.posinf	tstellar	2	-4/+0
2012-10-15	R600: use floor intrinsic instead of llvm.AMDIL.floor	tstellar	5	-5/+5
2012-10-15	R600: use llvm fabs intrinsic	tstellar	3	-5/+3
2012-10-15	R600: use llvm intrinsic for flog2	tstellar	3	-3/+2
2012-10-15	R600: add support for cos/sin intrinsic	tstellar	4	-14/+17
2012-10-15	R600: add a pattern for fsqrt	tstellar	1	-0/+3
2012-10-15	R600: Store channel index in the register's HWEncoding field	tstellar	8	-1117/+31
2012-10-11	AMDGPU: Fix lowering of UREM	tstellar	1	-5/+4
2012-10-11	AMDGPU: Fix build after merging of DataLayout changes	tstellar	3	-5/+5
2012-10-11	Merge master branch	tstellar	602	-8117/+12984
2012-10-10	R600: Fix typo in SETGE_UINT pattern	tstellar	1	-1/+1
2012-10-09	R600: Disable SI flow control again for now	tstellar	1	-1/+2
2012-10-09	R600: Handle reversed true/false values in selectcc	tstellar	2	-6/+26
2012-10-09	R600: Prefer lowering SELECT_CC to CND* instructions over SET* instructions	tstellar	2	-42/+66
2012-10-09	R600: Fix lowering of fcmp	tstellar	4	-7/+55
2012-10-09	R600: Add a pattern for: (selectcc i32, -1, i32, i32, SETGT)	tstellar	2	-0/+28
2012-10-09	R600: Add a comment explaining why we use TRUNC before FLT_TO_*INT	tstellar	1	-0/+10
2012-10-09	R600: Add store v4i32 test	tstellar	1	-0/+9
2012-10-09	R600: Add tests for a few vector operations	tstellar	7	-0/+106
2012-10-03	SI: Mark the V_CMPX* instructions as having side effects	tstellar	1	-0/+32
2012-10-03	R600: Handle more vector arithmetic instructions	tstellar	1	-0/+8
2012-10-03	R600: Implement getSetCCResultType in R600TargetLowering class	tstellar	2	-0/+8
2012-10-03	R600: Add support for v4i32 global stores	tstellar	1	-0/+6
2012-10-03	SI: Fix crash in unused register search in LowerFlowControl pass	tstellar	1	-4/+4
2012-10-03	SI: S_WAITCNT has side effects	tstellar	1	-0/+2
2012-10-03	SI: Set the section in the Asm Printer before emitting program info	tstellar	1	-1/+1
2012-10-03	SI: Fix bug in loops where iterators may be deleted	tstellar	2	-2/+4
2012-10-03	SI: Add sanity test	tstellar	1	-0/+37
2012-10-02	Merge master branch	tstellar	36	-121/+423
2012-10-02	R600: improve select_cc lowering to generate CND* more often	tstellar	5	-42/+110