R600: Use native operands for the MOV Instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166327 91177308-0d34-0410-b5e6-96231b3b80d8

7 files changed, 60 insertions, 47 deletions

diff --git a/lib/Target/AMDGPU/R600ISelLowering.cpp b/lib/Target/AMDGPU/R600ISelLowering.cpp
index 95294da901..8f4925dd0b 100644
--- a/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -81,36 +81,30 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
   case AMDGPU::SHADER_TYPE: break;
   case AMDGPU::CLAMP_R600:
     {
-      MachineInstr *NewMI =
-        BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
-               .addOperand(MI->getOperand(0))
-               .addOperand(MI->getOperand(1))
-               .addImm(0) // Flags
-               .addReg(AMDGPU::PRED_SEL_OFF);
+      MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
+                                                    AMDGPU::MOV,
+                                                    MI->getOperand(0).getReg(),
+                                                    MI->getOperand(1).getReg());
       TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
       break;
     }
   case AMDGPU::FABS_R600:
     {
-      MachineInstr *NewMI =
-        BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
-               .addOperand(MI->getOperand(0))
-               .addOperand(MI->getOperand(1))
-               .addImm(0) // Flags
-               .addReg(AMDGPU::PRED_SEL_OFF);
-      TII->addFlag(NewMI, 1, MO_FLAG_ABS);
+      MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
+                                                    AMDGPU::MOV,
+                                                    MI->getOperand(0).getReg(),
+                                                    MI->getOperand(1).getReg());
+      TII->addFlag(NewMI, 0, MO_FLAG_ABS);
       break;
     }
 
   case AMDGPU::FNEG_R600:
     {
-      MachineInstr *NewMI =
-        BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
-                .addOperand(MI->getOperand(0))
-                .addOperand(MI->getOperand(1))
-                .addImm(0) // Flags
-                .addReg(AMDGPU::PRED_SEL_OFF);
-      TII->addFlag(NewMI, 1, MO_FLAG_NEG);
+      MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
+                                                    AMDGPU::MOV,
+                                                    MI->getOperand(0).getReg(),
+                                                    MI->getOperand(1).getReg());
+      TII->addFlag(NewMI, 0, MO_FLAG_NEG);
     break;
     }
 
diff --git a/lib/Target/AMDGPU/R600InstrInfo.cpp b/lib/Target/AMDGPU/R600InstrInfo.cpp
index 6a4a47a4b2..b0eb128999 100644
--- a/lib/Target/AMDGPU/R600InstrInfo.cpp
+++ b/lib/Target/AMDGPU/R600InstrInfo.cpp
@@ -54,23 +54,22 @@ R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
       && AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
     for (unsigned I = 0; I < 4; I++) {
       unsigned SubRegIndex = RI.getSubRegFromChannel(I);
-      BuildMI(MBB, MI, DL, get(AMDGPU::MOV))
-              .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define)
-              .addReg(RI.getSubReg(SrcReg, SubRegIndex))
-              .addImm(0) // Flag
-              .addReg(0) // PREDICATE_BIT
-              .addReg(DestReg, RegState::Define | RegState::Implicit);
+      buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
+                              RI.getSubReg(DestReg, SubRegIndex),
+                              RI.getSubReg(SrcReg, SubRegIndex))
+                              .addReg(DestReg,
+                                      RegState::Define | RegState::Implicit);
     }
   } else {
 
-    /* We can't copy vec4 registers */
+    // We can't copy vec4 registers
     assert(!AMDGPU::R600_Reg128RegClass.contains(DestReg)
            && !AMDGPU::R600_Reg128RegClass.contains(SrcReg));
 
-    BuildMI(MBB, MI, DL, get(AMDGPU::MOV), DestReg)
-      .addReg(SrcReg, getKillRegState(KillSrc))
-      .addImm(0) // Flag
-      .addReg(0); // PREDICATE_BIT
+    MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
+                                                  DestReg, SrcReg);
+    NewMI->getOperand(getOperandIdx(*NewMI, R600Operands::SRC0))
+                                    .setIsKill(KillSrc);
   }
 }
 
@@ -475,6 +474,28 @@ unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
   return 2;
 }
 
+MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB,
+                                                  MachineBasicBlock::iterator I,
+                                                  unsigned Opcode,
+                                                  unsigned DstReg,
+                                                  unsigned Src0Reg) const
+{
+  return BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode), DstReg)
+    .addImm(1)        // $write
+    .addImm(0)        // $omod
+    .addImm(0)        // $dst_rel
+    .addImm(0)        // $dst_clamp
+    .addReg(Src0Reg)  // $src0
+    .addImm(0)        // $src0_neg
+    .addImm(0)        // $src0_rel
+    .addImm(0)        // $src0_abs
+    //XXX: The r600g finalizer expects this to be 1, once we've moved the
+    //scheduling to the backend, we can change the default to 0.
+    .addImm(1)        // $last
+    .addReg(AMDGPU::PRED_SEL_OFF) // $pred_sel
+    .addImm(0);        // $literal
+}
+
 int R600InstrInfo::getOperandIdx(const MachineInstr &MI,
                                  R600Operands::Ops Op) const
 {
diff --git a/lib/Target/AMDGPU/R600InstrInfo.h b/lib/Target/AMDGPU/R600InstrInfo.h
index 7c903c1084..33899ce6a9 100644
--- a/lib/Target/AMDGPU/R600InstrInfo.h
+++ b/lib/Target/AMDGPU/R600InstrInfo.h
@@ -110,6 +110,16 @@ namespace llvm {
   virtual int getInstrLatency(const InstrItineraryData *ItinData,
                               SDNode *Node) const { return 1;}
 
+  ///buildDefaultInstruction - This function returns a MachineInstr with
+  /// all the instruction modifiers initialized to their default values.
+  /// You can use this function to avoid manually specifying each instruction
+  /// modifier operand when building a new instruction.
+  MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
+                                              MachineBasicBlock::iterator I,
+                                              unsigned Opcode,
+                                              unsigned DstReg,
+                                              unsigned Src0Reg) const;
+
   /// getOperandIdx - Get the index of Op in the MachineInstr.  Returns -1
   /// if the Instruction does not contain the specified Op.
   int getOperandIdx(const MachineInstr &MI, R600Operands::Ops Op) const;
diff --git a/lib/Target/AMDGPU/R600Instructions.td b/lib/Target/AMDGPU/R600Instructions.td
index 23e88b334d..176e524e8e 100644
--- a/lib/Target/AMDGPU/R600Instructions.td
+++ b/lib/Target/AMDGPU/R600Instructions.td
@@ -514,19 +514,7 @@ def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>;
 def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>;
 def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>;
 
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
-
-def MOV : InstR600 <0x19, (outs R600_Reg32:$dst),
-                          (ins R600_Reg32:$src0, i32imm:$flags,
-                               R600_Pred:$p),
-                          "MOV $dst, $src0", [], AnyALU> {
-  let FlagOperandIdx = 2;
-  bits<7> dst;
-  bits<9> src0;
-  let Inst{8-0}   = src0;
-  let Inst{49-39} = op_code;
-  let Inst{59-53} = dst;
-}
+def MOV : R600_1OP <0x19, "MOV", []>;
 
 class MOV_IMM <ValueType vt, Operand immType> : InstR600 <0x19,
   (outs R600_Reg32:$dst),
@@ -543,7 +531,6 @@ class MOV_IMM <ValueType vt, Operand immType> : InstR600 <0x19,
   let Inst{59-53} = dst;
 }
 
-} // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
 def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
 def : Pat <
   (imm:$val),
diff --git a/test/CodeGen/R600/fabs.ll b/test/CodeGen/R600/fabs.ll
index 3911a70086..0407533eaa 100644
--- a/test/CodeGen/R600/fabs.ll
+++ b/test/CodeGen/R600/fabs.ll
@@ -1,6 +1,6 @@
 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
-;CHECK: MOV T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;CHECK: MOV T{{[0-9]+\.[XYZW], \|T[0-9]+\.[XYZW]\|}}
 
 define void @test() {
    %r0 = call float @llvm.R600.load.input(i32 0)
diff --git a/test/CodeGen/R600/fcmp.ll b/test/CodeGen/R600/fcmp.ll
index 4a54def50d..1dcd07c0b3 100644
--- a/test/CodeGen/R600/fcmp.ll
+++ b/test/CodeGen/R600/fcmp.ll
@@ -1,7 +1,7 @@
 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
 ;CHECK: SETE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: MOV T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;CHECK: MOV T{{[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
 ;CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 
 define void @test(i32 addrspace(1)* %out, float addrspace(1)* %in) {
diff --git a/test/CodeGen/R600/fsub.ll b/test/CodeGen/R600/fsub.ll
index e938df2aba..0ec1c376df 100644
--- a/test/CodeGen/R600/fsub.ll
+++ b/test/CodeGen/R600/fsub.ll
@@ -1,5 +1,6 @@
 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
+; CHECK: MOV T{{[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
 ; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 
 define void @test() {