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2017-04-28i965: Don't allocate uniform space for samplersHEADmasterMatt Turner1-1/+3
Samplers are encoded into the instruction word, so there's no need to make space in the uniform file. Previously matrix_columns and vector_elements were set to 0, making this else case a no-op. Commit 75a31a20af26 changed that, causing malloc corruption in thousands of tests on i965. Fixes: 75a31a20af26 ("glsl: set vector_elements to 1 for samplers")
2017-04-27glsl: set vector_elements to 1 for samplersSamuel Pitoiset2-16/+6
I don't see any reasons why vector_elements is 1 for images and 0 for samplers. This increases consistency and allows to clean up some code a bit. This will also help for ARB_bindless_texture. No piglit regressions with RadeonSI. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-27clover: Fix build since clang r301442Jan Vesely2-1/+3
v2: rename default_ik -> ik_opencl Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2017-04-27disk_cache: use block size rather than file sizeTimothy Arceri1-5/+11
The majority of cache files are less than 1kb this resulted in us greatly miscalculating the amount of disk space used by the cache. Using the number of blocks allocated to the file is more conservative and less likely to cause issues. This change will result in cache sizes being miscalculated further until old items added with the previous calculation have all been removed. However I don't see anyway around that, the previous patch should help limit that problem. Cc: "17.1" <mesa-stable@lists.freedesktop.org> Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
2017-04-27disk_cache: reduce default cache size to 5% of filesystemTimothy Arceri1-2/+2
Modern disks are extremely large and are only going to get bigger. Usage has shown frequent Mesa upgrades can result in the cache growing very fast i.e. wasting a lot of disk space unnecessarily. 5% seems like a more reasonable default. Cc: "17.1" <mesa-stable@lists.freedesktop.org> Acked-by: Michel Dänzer <michel.daenzer@amd.com>
2017-04-27radeon/ac: remove assert causing regressionDave Airlie1-1/+0
This assert wasn't in the original radeonsi code but I added it without totally understanding the original code, it caused some regressions in variable-indexing tessellation shaders. Fixes: e2659176 radeonsi/ac: move vertex export remove to common code. Reported-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-27radeon/ac: fix build on llvm 3.8.1Dave Airlie1-0/+1
Add missing include to fix build. Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-27nvc0: Enable compute support for PascalBoyan Ding3-4/+7
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-04-27nvc0: Add new launch descriptor format for GP100Boyan Ding2-34/+197
v2: Also handle the the new format in indirect dispatch Use compute class check instead of chipset check Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-04-27nvc0: Fix index of unk fields in nve4_cp_launch_descBoyan Ding1-2/+2
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-04-27nouveau: Fix indentation of maxwell compute class definitionsBoyan Ding1-2/+2
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-04-27anv: Don't place scratch buffers above the 32-bit boundaryJason Ekstrand1-0/+19
This fixes rendering corruptions in DOOM. Hopefully, it will also make Jenkins a bit more stable as we've been seeing some random failures and GPU hangs ever since turning on 48bit. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100620 Fixes: 651ec926fc1 "anv: Add support for 48-bit addresses" Tested-by: Grazvydas Ignotas <notasas@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Cc: "17.1" <mesa-stable@lists.freedesktop.org>
2017-04-27radv/ac: eliminate unused vertex shader outputs. (v2)Dave Airlie3-21/+45
This is ported from radeonsi, and I can see at least one Talos shader drops an export due to this, and saves some VGPR usage. v2: use shared code. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-27radeonsi/ac: move vertex export remove to common code.Dave Airlie8-164/+235
This code can be shared by radv, we bump the max to VARYING_SLOT_MAX here, but that shouldn't have too much fallout. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-27radv: fix regression in descriptor set freeing.Dave Airlie1-1/+1
Since the host pool changes, Fixes: dEQP-VK.api.descriptor_pool.out_of_pool_memory Fixes: 126d5ad "radv: Use host memory pool for non-freeable descriptors." Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-27glsl: remove duplicate validationTimothy Arceri1-15/+0
Varying types have already been validated in apply_type_qualifier_to_variable() by this point. Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-04-27glsl: use without_array() rather than get_scalar_type()Timothy Arceri1-1/+1
Here get_scalar_type() was just being use to remove the array after that we converted it back to base_type anyway so just use the without_array() helper. Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2017-04-26svga: fix vertex buffer binding issueBrian Paul1-2/+29
When we ran Viewperf11's Maya-03 test 3 we saw warnings about flushing the command buffer with mapped buffers. This happened when transitioning from hardware rendering to a 'draw' fallback path. The problem is the util_set_vertex_buffers_count() function doesn't do exactly what we want in svga_hwtnl_vertex_buffers(). In a case such as dst_count=2, dst={bufA, bufB}, count=1 and src={bufC}, when the function returns we'll have dst_count=2 and dst={bufC, bufB}. What we really want is dst_count=1 and dst={bufC, NULL}. As it was, we were telling the svga device that there were two vertex buffers when in fact we really only needed one for the subsequent drawing command. In this particular case, we first did hardware drawing with {bufA, bufB} then we transitioned to the 'draw' module, consuming vertex data from bufA and bufB and writing the new vertex data to bufC. bufA and bufB are mapped for reading when we flush the command buffer but should not be referenced by the command buffer. The above change fixes that. No Piglit regressions. Also tested with Viewperf, Google Earth, Heaven, etc. VMware bug 1842059 Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-04-26gallium/util: reduce util_snprintf() calls in debug_flush_might_flush_cb()Brian Paul1-5/+6
We only need to construct the debug message if the mapped_sync flag is set. This should make the function faster since the flag is usually false. Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-04-26gallium/util: add some comments in u_debug_flush.cBrian Paul1-0/+15
Trivial. Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-04-26svga: Removed the unused label 'done' in svga_validate_surface_view()Charmaine Lee1-1/+0
Trivial fix
2017-04-26svga: use the winsys interface to invalidate surfaceCharmaine Lee1-5/+1
Instead of directly sending the InvalidateGBSurface command, this patch uses the invalidate_surface interface. Fixes Linux VM piglit failures including ext_texture_array-gen-mipmap, fbo-generatemipmap-array S3TC_DXT1 Reviewed-by: Brian Paul <brianp@vmware.com>
2017-04-26svga: fix format for screen targetCharmaine Lee1-0/+26
This patch revises the fix in commit 606f13afa31c9f041a68eb22cc32112ce813f944 to properly translate the surface format for screen target. Instead of changing the svga format for PIPE_FORMAT_B5G6R5_UNORM to SVGA3D_R5G6B5 for all texture surfaces, this patch only restricts SVGA3D_R5G6B5 for screen target surfaces. This avoids rendering failures when specify a non-vgpu10 format in a vgpu10 context with software renderer. Fixes piglit failures spec@!opengl 1.1@draw-pixels, spec@!opengl 1.1@teximage-colors gl_r3_g3_b2 spec@!opengl 1.1@texwrap formats Tested Xorg with 16bits depth. Also tested with MTT piglit, MTT glretrace. Reviewed-by: Brian Paul <brianp@vmware.com>
2017-04-26svga: cache the backing surface handle in the texture objectCharmaine Lee5-10/+57
CinebenchR15 not only binds the same texture for rendering and sampling, it actually changes the framebuffer buffer attachment very often, causing a lot of backed surface view to be created and a lot of surface copies to be done. This patch caches the backed surface handle in the texture resource and allows the backed surface view to reuse the backed surface handle. With this patch, the number of backed surface view reduces from 1312 to 3. Unfortunately, this does not eliminate all the surface copies. There are still surface copies involved when we switch from original to backed surface handle for rendering. Tested with CinebenchR15, NobelClinicianViewer, Turbine, Lightsmark2008, MTT glretrace, MTT piglit. Reviewed-by: Brian Paul <brianp@vmware.com>
2017-04-26svga: Update the backing resource only if neededCharmaine Lee2-3/+14
This patch adds a timestamp in svga_surface structure to keep track of when the backing surface is last sync with the original resource. This helps to avoid unnecessary surface copy from the original resource to the backing surface if the original resource has not since been modified. This reduces the amount of surface copy with CinebenchR15. Tested with CinebenchR15, mtt glretrace. Reviewed-by: Brian Paul <brianp@vmware.com>
2017-04-26svga: Set the surface dirty bit for the right surface viewCharmaine Lee1-5/+19
For VGPU10, we will render to a backed surface view when the same resource is used for rendering and sampling. In this case, we will mark the dirty bit for the backed surface view. Reviewed-by: Brian Paul <brianp@vmware.com>
2017-04-26svga: Move rendertarget view related fields to hw_clear stateCharmaine Lee4-17/+18
This patch moves the rendertarget view related fields from svga_hw_draw_state to svga_hw_clear_state where all the hw framebuffer related state resides. Reviewed-by: Brian Paul <brianp@vmware.com>
2017-04-26svga: Move setting the rendered_to flags to framebuffer emit timeCharmaine Lee2-18/+28
Instead of setting the rendered_to flags at set time, this patch moves the setting of the flags to framebuffer emit time. Reviewed-by: Brian Paul <brianp@vmware.com>
2017-04-26svga: add const qualifiers on svga_check_sampler_view_resource_collision()Brian Paul2-4/+4
We don't change any of the argument objects. Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-04-26svga: improve surface view debug messagesBrian Paul1-4/+5
The old ones were somewhat cryptic. Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-04-26svga: add DEBUG_SAMPLERSBrian Paul3-1/+4
The debug output in svga_create_sampler_state() was controlled by DEBUG_VIEWS but that's not consistent with the other debug output for sampler views. Create/use a new debug flag just for this. Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-04-26svga: fail screen creation if HW version is too oldBrian Paul1-0/+7
Tested by verifying 3D acceleration works with HWv8 but not earlier. For HWv7 and older we get the GDI Generic renderer. Reviewed-by: Neha Bhende<bhenden@vmware.com> Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-04-26winsys/svga: fix error path when kernel is not able to create surfaceDeepak Rawat1-15/+18
If for some reason kernel is not able to create surface, when no buffer was provided the function vmw_svga_winsys_surface_create should return NULL. This patch fixes the issue where the code was not following the clean up path in case of error, which used to cause SIGSEGV. Reviewed-by: Sinclair Yeh <syeh@vmware.com>
2017-04-26draw: whitespace fixes in draw_pipe_vbuf.cBrian Paul1-104/+89
Remove trailing whitespace, fix formatting, etc. Trivial.
2017-04-26st/mesa: minor clean-ups in st_update_renderbuffer_surface()Brian Paul1-9/+8
Remove unneeded parens. Add const qualifiers. Move var decls closer to where they're used. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Neha Bhende<bhenden@vmware.com>
2017-04-26nv50,nvc0: disable the TGSI merge registers passSamuel Pitoiset2-2/+4
shader-db results on GK106 (Thanks Karol): total instructions in shared programs : 3931608 -> 3929463 (-0.05%) total gprs used in shared programs : 481255 -> 479014 (-0.47%) total local used in shared programs : 27481 -> 27381 (-0.36%) total bytes used in shared programs : 36031256 -> 36011120 (-0.06%) local gpr inst bytes helped 14 1471 1309 1309 hurt 1 88 384 384 Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-04-26radeonsi: disable the TGSI merge registers passSamuel Pitoiset1-1/+1
47109 shaders in 29632 tests Totals: SGPRS: 1917364 -> 1916620 (-0.04 %) VGPRS: 1165802 -> 1165202 (-0.05 %) Spilled SGPRs: 1880 -> 1843 (-1.97 %) Spilled VGPRs: 70 -> 65 (-7.14 %) Private memory VGPRs: 1184 -> 1184 (0.00 %) Scratch size: 1312 -> 1308 (-0.30 %) dwords per thread Code Size: 60211356 -> 60192268 (-0.03 %) bytes LDS: 1077 -> 1077 (0.00 %) blocks Max Waves: 428597 -> 428674 (0.02 %) Wait states: 0 -> 0 (0.00 %) Totals from affected shaders: SGPRS: 238173 -> 237429 (-0.31 %) VGPRS: 149556 -> 148956 (-0.40 %) Spilled SGPRs: 1263 -> 1226 (-2.93 %) Spilled VGPRs: 25 -> 20 (-20.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 20 -> 16 (-20.00 %) dwords per thread Code Size: 10457904 -> 10438816 (-0.18 %) bytes LDS: 50 -> 50 (0.00 %) blocks Max Waves: 41283 -> 41360 (0.19 %) Wait states: 0 -> 0 (0.00 %) Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-26st/glsl_to_tgsi: disable the merge registers pass conditionallySamuel Pitoiset1-1/+6
The main goal of this pass to merge temporary registers in order to reduce the total number of registers and also to produce optimal TGSI code. In fact, compilers seem to be confused when temporary variables are already merged, maybe because it's done too early in the process. Skipping the pass, reduce both the register pressure and the code size, at least for Nouveau and RadeonSI because they have a real backend compiler. Found by luck while fixing an issue in the TGSI dead code elimination pass which affects tex instructions with bindless samplers. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-26gallium: add PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERSSamuel Pitoiset15-0/+21
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-26radeonsi: use unsynchronized transfers for shader binary uploadsSamuel Pitoiset1-1/+2
Because the buffer is new, it can't be referenced by any CS. This can save few CPU cycles by skipping the whole PIPE_TRANSFER_UNSYNCHRONIZED if in amdgpu_bo_map(). Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-26radeonsi: turn si_shader_key::mono into a non-unionMarek Olšák3-15/+11
A merged LS-HS shader needs both fix_fetch and inputs_to_copy for compilation. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-26radeonsi: adjust ESGS ring buffer size computation on VIMarek Olšák1-1/+4
Cc: 17.0 17.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-26radeonsi/gfx9: don't set deprecated field PARTIAL_ES_WAVE_ONMarek Olšák1-2/+3
Cc: 17.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-26radeonsi/gfx9: set MAX_PRIMGRP_IN_WAVE in the correct registerMarek Olšák2-1/+5
Cc: 17.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-26radeonsi/gfx9: add a workaround for viewing a slice of 3D as a 2D imageMarek Olšák1-8/+22
Cc: 17.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-26radeonsi/gfx9: fix 1D array shader imagesMarek Olšák1-0/+1
Cc: 17.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-26radeonsi/gfx9: fix most things wrong with shader imagesMarek Olšák2-12/+24
There are 2 major hw changes: - The address must always point to the address of level 0. GFX9 tiling modes don't allow binding to a non-0 level. - 3D must always be bound as 3D, because 2D and 3D use entirely different tiling modes, and the texture target determines which set of modes is used. Cc: 17.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-26radeonsi/gfx9: fix texture buffer objects and image buffers with IDXEN==0Marek Olšák1-1/+34
Cc: 17.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-26configure: print LDFLAGS alongside CFLAGS & co.Eric Engestrom1-1/+3
Signed-off-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-26mesa: tidy up left over APPLE_vertex_array_object semanticsTimothy Arceri4-43/+9
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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