diff options
| author | Marek Olšák <marek.olsak@amd.com> | 2017-04-22 14:47:03 +0200 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2017-04-26 13:08:05 +0200 |
| commit | 3f2a0649abc982fe5de647a96fbe354aa9e41a59 (patch) | |
| tree | 76b71731f3ff02c7c547d44e99a92b7f2c495cf5 | |
| parent | 80814819c28353a38c03d4cdba39983b8cf260ac (diff) | |
radeonsi: adjust ESGS ring buffer size computation on VI
Cc: 17.0 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_shaders.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index 34cd6d46315..3a604eb660a 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -2115,7 +2115,10 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx) unsigned num_se = sctx->screen->b.info.max_se; unsigned wave_size = 64; unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */ - unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */ + /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16. + * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2). + */ + unsigned gs_vertex_reuse = (sctx->b.chip_class >= VI ? 32 : 16) * num_se; unsigned alignment = 256 * num_se; /* The maximum size is 63.999 MB per SE. */ unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se; |