Finish IMM / constantpool support

Signed-off-by: Hans de Goede <hdegoede@redhat.com>

8 files changed, 174 insertions, 12 deletions

diff --git a/lib/Target/TGSI/MCTargetDesc/CMakeLists.txt b/lib/Target/TGSI/MCTargetDesc/CMakeLists.txt
index 5ec827effe1..5d6528f38dc 100644
--- a/lib/Target/TGSI/MCTargetDesc/CMakeLists.txt
+++ b/lib/Target/TGSI/MCTargetDesc/CMakeLists.txt
@@ -1,6 +1,8 @@
 add_llvm_library(LLVMTGSIDesc
-  TGSIMCTargetDesc.cpp
+  TGSIASMStreamer.cpp
   TGSIMCInstPrinter.cpp
+  TGSIMCTargetDesc.cpp
+  TGSITargetStreamer.cpp
   )
 
 add_dependencies(LLVMTGSIDesc LLVMTGSIInfo)
diff --git a/lib/Target/TGSI/MCTargetDesc/TGSIASMStreamer.cpp b/lib/Target/TGSI/MCTargetDesc/TGSIASMStreamer.cpp
new file mode 100644
index 00000000000..c6c5489708a
--- /dev/null
+++ b/lib/Target/TGSI/MCTargetDesc/TGSIASMStreamer.cpp
@@ -0,0 +1,57 @@
+//===- lib/MC/TGSIELFStreamer.cpp - ELF Object Output for TGSI --------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "TGSITargetStreamer.h"
+
+#include "llvm/IR/Constants.h"
+#include "llvm/Support/FormattedStream.h"
+#include "llvm/Support/raw_ostream.h"
+
+namespace llvm {
+
+class TGSITargetAsmStreamer : public TGSITargetStreamer {
+   formatted_raw_ostream &OS;
+   MCInstPrinter &InstPrinter;
+   bool IsVerboseAsm;
+
+public:
+   TGSITargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS,
+                        MCInstPrinter &InstPrinter, bool VerboseAsm);
+   virtual void EmitConstantPoolEntry(const MachineConstantPoolEntry &CPE) override;
+};
+
+TGSITargetAsmStreamer::TGSITargetAsmStreamer(MCStreamer &S,
+                                             formatted_raw_ostream &OS,
+                                             MCInstPrinter &InstPrinter,
+                                             bool VerboseAsm)
+    : TGSITargetStreamer(S), OS(OS), InstPrinter(InstPrinter),
+      IsVerboseAsm(VerboseAsm) {}
+
+void TGSITargetAsmStreamer::EmitConstantPoolEntry(
+                                       const MachineConstantPoolEntry &CPE) {
+   assert(!CPE.isMachineConstantPoolEntry());
+
+   if (const ConstantInt *CI = dyn_cast<ConstantInt>(CPE.Val.ConstVal)) {
+      assert(CI->getBitWidth() == 32);
+      OS << "IMM UINT32 { " << CI->getZExtValue() << ", 0, 0, 0 }\n";
+   }
+}
+
+MCTargetStreamer *createTGSITargetAsmStreamer(MCStreamer &S,
+                                              formatted_raw_ostream &OS,
+                                              MCInstPrinter *InstPrint,
+                                              bool isVerboseAsm) {
+   return new TGSITargetAsmStreamer(S, OS, *InstPrint, isVerboseAsm);
+}
+
+MCTargetStreamer *createTGSINullTargetStreamer(MCStreamer &S) {
+   return new TGSITargetStreamer(S);
+}
+
+} // namespace llvm.
diff --git a/lib/Target/TGSI/MCTargetDesc/TGSIASMStreamer.h b/lib/Target/TGSI/MCTargetDesc/TGSIASMStreamer.h
new file mode 100644
index 00000000000..331868cfd61
--- /dev/null
+++ b/lib/Target/TGSI/MCTargetDesc/TGSIASMStreamer.h
@@ -0,0 +1,26 @@
+//===-------------------- TGSIASMStreamer.h -------------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_TGSI_MCTARGETDESC_TGSIASMSTREAMER_H
+#define LLVM_LIB_TARGET_TGSI_MCTARGETDESC_TGSIASMSTREAMER_H
+
+#include "llvm/MC/MCELFStreamer.h"
+
+namespace llvm {
+
+MCTargetStreamer *createTGSITargetAsmStreamer(MCStreamer &S,
+                                             formatted_raw_ostream &OS,
+                                             MCInstPrinter *InstPrint,
+                                             bool isVerboseAsm);
+                                             
+MCTargetStreamer *createTGSINullTargetStreamer(MCStreamer &S);
+
+} // namespace llvm.
+
+#endif
diff --git a/lib/Target/TGSI/MCTargetDesc/TGSIMCInstPrinter.cpp b/lib/Target/TGSI/MCTargetDesc/TGSIMCInstPrinter.cpp
index d8f049df806..db8c1091fbd 100644
--- a/lib/Target/TGSI/MCTargetDesc/TGSIMCInstPrinter.cpp
+++ b/lib/Target/TGSI/MCTargetDesc/TGSIMCInstPrinter.cpp
@@ -39,7 +39,7 @@ namespace {
 
       void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
    private:
-      bool isInputOperand(const MCInst *mi, unsigned op_idx);
+      bool requiresSwizzleSuffix(const MCInst *mi, unsigned op_idx, bool isImm);
    };
 }
 
@@ -55,12 +55,14 @@ void TGSIMCInstPrinter::printRegName(raw_ostream &os, unsigned reg) const {
    os << getRegisterName(reg);
 }
 
-bool TGSIMCInstPrinter::isInputOperand(const MCInst *mi, unsigned op_idx)
+bool TGSIMCInstPrinter::requiresSwizzleSuffix(const MCInst *mi, unsigned op_idx,
+                                              bool isImm)
 {
    const char *name = MII.getName(mi->getOpcode());
 
-   if (name[0] == 'S' && name[1] == 'T')
-      return true; /* Both operands for a store are input operands */
+   if ((name[0] == 'S' && name[1] == 'T' && op_idx == 0) ||
+       (name[0] == 'L' && name[1] == 'D' && op_idx == 1))
+         return !isImm;
 
    return op_idx >= 1;
 }
@@ -70,7 +72,7 @@ void TGSIMCInstPrinter::printOperand(const MCInst *mi, unsigned op_idx,
    const MCOperand &op = mi->getOperand(op_idx);
 
    if (op.isReg()) {
-      if (isInputOperand(mi, op_idx)) {
+      if (requiresSwizzleSuffix(mi, op_idx, false)) {
          MCSuperRegIterator Supers(op.getReg(), &MRI);
          if (Supers.isValid()) {
             /* Subreg source operand, print superreg name +
@@ -88,11 +90,11 @@ void TGSIMCInstPrinter::printOperand(const MCInst *mi, unsigned op_idx,
          }
       }
       os << getRegisterName(op.getReg());
-   } else if (op.isImm())
-      os << op.getImm();
-   else if (op.isFPImm())
-      os << op.getFPImm();
-   else if (op.isExpr())
+   } else if (op.isImm()) {
+      os << "IMM[" << op.getImm() << "]";
+      if (requiresSwizzleSuffix(mi, op_idx, true))
+         os << ".xxxx";
+   } else if (op.isExpr())
       os << *op.getExpr();
    else
       assert(0);
diff --git a/lib/Target/TGSI/MCTargetDesc/TGSIMCTargetDesc.cpp b/lib/Target/TGSI/MCTargetDesc/TGSIMCTargetDesc.cpp
index edbb03b7cb4..ecb184cc86c 100644
--- a/lib/Target/TGSI/MCTargetDesc/TGSIMCTargetDesc.cpp
+++ b/lib/Target/TGSI/MCTargetDesc/TGSIMCTargetDesc.cpp
@@ -11,6 +11,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "TGSIASMStreamer.h"
 #include "TGSIMCTargetDesc.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
@@ -67,4 +68,9 @@ extern "C" void LLVMInitializeTGSITargetMC() {
                                            createTGSIMCSubtargetInfo);
    TargetRegistry::RegisterMCInstPrinter(TheTGSITarget,
                                          createTGSIMCInstPrinter);
+
+   TargetRegistry::RegisterAsmTargetStreamer(TheTGSITarget,
+                                             createTGSITargetAsmStreamer);
+   TargetRegistry::RegisterNullTargetStreamer(TheTGSITarget,
+                                              createTGSINullTargetStreamer);
 }
diff --git a/lib/Target/TGSI/MCTargetDesc/TGSITargetStreamer.cpp b/lib/Target/TGSI/MCTargetDesc/TGSITargetStreamer.cpp
new file mode 100644
index 00000000000..3e596c448bd
--- /dev/null
+++ b/lib/Target/TGSI/MCTargetDesc/TGSITargetStreamer.cpp
@@ -0,0 +1,23 @@
+//===- TGSITargetStreamer.cpp - TGSITargetStreamer class --*- C++ -*---------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the TGSITargetStreamer class.
+//
+//===----------------------------------------------------------------------===//
+#include "TGSITargetStreamer.h"
+
+using namespace llvm;
+
+TGSITargetStreamer::TGSITargetStreamer(MCStreamer &S)
+    : MCTargetStreamer(S) {}
+
+TGSITargetStreamer::~TGSITargetStreamer() {}
+
+void TGSITargetStreamer::EmitConstantPoolEntry(
+                                  const MachineConstantPoolEntry &CPE) {}
diff --git a/lib/Target/TGSI/MCTargetDesc/TGSITargetStreamer.h b/lib/Target/TGSI/MCTargetDesc/TGSITargetStreamer.h
new file mode 100644
index 00000000000..d9dc7a8d095
--- /dev/null
+++ b/lib/Target/TGSI/MCTargetDesc/TGSITargetStreamer.h
@@ -0,0 +1,28 @@
+//===--------------------- TGSITargetStreamer.h ---------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_TGSI_MCTARGETDESC_TGSITARGETSTREAMER_H
+#define LLVM_LIB_TARGET_TGSI_MCTARGETDESC_TGSITARGETSTREAMER_H
+
+#include "llvm/CodeGen/MachineConstantPool.h"
+#include "llvm/MC/MCStreamer.h"
+
+namespace llvm {
+
+class TGSITargetStreamer : public MCTargetStreamer {
+public:
+   TGSITargetStreamer(MCStreamer &S);
+   ~TGSITargetStreamer() override;
+
+   virtual void EmitConstantPoolEntry(const MachineConstantPoolEntry &CPE);
+};
+
+} // namespace llvm.
+
+#endif
diff --git a/lib/Target/TGSI/TGSIAsmPrinter.cpp b/lib/Target/TGSI/TGSIAsmPrinter.cpp
index 8a6f9febed5..ccf0b4b30c0 100644
--- a/lib/Target/TGSI/TGSIAsmPrinter.cpp
+++ b/lib/Target/TGSI/TGSIAsmPrinter.cpp
@@ -16,8 +16,10 @@
 #include "TGSI.h"
 #include "TGSIInstrInfo.h"
 #include "TGSITargetMachine.h"
+#include "MCTargetDesc/TGSITargetStreamer.h"
 
 #include "llvm/CodeGen/AsmPrinter.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCStreamer.h"
@@ -48,6 +50,7 @@ namespace {
       virtual void EmitInstruction(const MachineInstr *mi);
       virtual void EmitFunctionBodyStart();
       virtual void EmitFunctionBodyEnd();
+      virtual void EmitConstantPool() override;
 
       void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
       void printInstruction(const MachineInstr *MI, raw_ostream &OS);
@@ -104,10 +107,12 @@ static void LowerMachineInstrToMCInst(const MachineInstr *mi, MCInst &mci,
          case MachineOperand::MO_Immediate:
             mco = MCOperand::createImm(mo.getImm());
             break;
+/*          mco = MCOperand::createExpr(MCSymbolRefExpr::create(
+                     ap.GetCPISymbol(mo.getImm()), ap.OutContext));
          case MachineOperand::MO_FPImmediate:
             mco = MCOperand::createFPImm(mo.getFPImm()->getValueAPF()
                                          .convertToFloat());
-            break;
+            break; */
          case MachineOperand::MO_MachineBasicBlock:
             mco = MCOperand::createExpr(MCSymbolRefExpr::create
                                         (mo.getMBB()->getSymbol(), ap.OutContext));
@@ -151,6 +156,19 @@ void TGSIAsmPrinter::EmitFunctionBodyEnd() {
    OutStreamer->EmitInstruction(mci, getSubtargetInfo());
 }
 
+void TGSIAsmPrinter::EmitConstantPool() {
+   const MachineConstantPool *MCP = MF->getConstantPool();
+   const std::vector<MachineConstantPoolEntry> &CP = MCP->getConstants();
+
+   if (CP.empty()) return;
+
+   MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
+   TGSITargetStreamer &TTS = static_cast<TGSITargetStreamer &>(TS);
+
+   for (unsigned i = 0; i < CP.size(); i++)
+      TTS.EmitConstantPoolEntry(CP[i]);
+}
+
 extern "C" void LLVMInitializeTGSIAsmPrinter() {
    RegisterAsmPrinter<TGSIAsmPrinter> X(TheTGSITarget);
 }