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2018-10-10intel/compiler: Fix nir_op_b2[fi] with 64-bit result on Gen8 LP and Gen9 LPHEADmasterJason Ekstrand1-5/+5
Several of the Atom GPUs have additional restrictions on alignment when moving < 64-bit source to a 64-bit destination. All of the nir_op_*2*64 code generation paths respected this, but nir_op_b2[fi] did not. Previous to commit a68dd47b911 it was not possible to generate such an instruction from the GLSL path. It may have been possible from SPIR-V, but it's not clear. The aforementioned patch converts a 64-bit nir_op_fsign into a sequence of operations including a nir_op_b2f with a 64-bit result. This "just works" everywhere except these Atom parts. This problem was not detected during normal CI testing because the Atom parts are not included in developer builds. v2 (idr): Make the patch compile, and make some cosmetic changes. Add a commit message. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108319 Fixes: a68dd47b911 "nir/algebraic: Simplify fsat of fsign"
2018-10-09intel/compiler: Don't handle fsign.satIan Romanick2-23/+3
No shader-db or CI changes on any Intel platform. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
2018-10-09nir/algebraic: Simplify fsat of fsignIan Romanick1-0/+1
These allows us to not support fsign.sat in the Intel compiler backend, and that will simplify some later changes. No shader-db changes on any Intel platform. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
2018-10-09nir/algebraic: sign(x)*x*x is abs(x)*xIan Romanick1-0/+5
shader-db results: All Gen7+ platforms had similar results. (Skylake shown) total instructions in shared programs: 15106023 -> 15105981 (<.01%) instructions in affected programs: 300 -> 258 (-14.00%) helped: 6 HURT: 0 helped stats (abs) min: 7 max: 7 x̄: 7.00 x̃: 7 helped stats (rel) min: 14.00% max: 14.00% x̄: 14.00% x̃: 14.00% 95% mean confidence interval for instructions value: -7.00 -7.00 95% mean confidence interval for instructions %-change: -14.00% -14.00% Instructions are helped. total cycles in shared programs: 566050327 -> 566050075 (<.01%) cycles in affected programs: 2826 -> 2574 (-8.92%) helped: 6 HURT: 0 helped stats (abs) min: 40 max: 44 x̄: 42.00 x̃: 42 helped stats (rel) min: 8.89% max: 8.94% x̄: 8.92% x̃: 8.92% 95% mean confidence interval for cycles value: -44.30 -39.70 95% mean confidence interval for cycles %-change: -8.95% -8.88% Cycles are helped. No changes on Gen6 or earlier. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
2018-10-09nir: Add helper functions to get the instruction that generated a nir_srcIan Romanick1-0/+23
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
2018-10-09svga: change svga_destroy_shader_variant() to return voidBrian Paul5-23/+6
svga_destroy_shader_variant() itself flushes and retries the command if there's a failure. So no need for the callers to do it. Other callers of the function were already ignoring the return value. This also fixes a corner-case double-free reported by Coverity (and reported by Dave Airlie). Tested with various OpenGL apps. Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2018-10-09meson: Don't build glsl compiler tests unless OpenGL is enabledDylan Baker2-2/+2
Since there are no other users of the glsl compiler. Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-10-09meson: Only build gallium state tracker tests with shared_glapiDylan Baker1-1/+1
This has always been a requirement, it's just somehow been missed in the meson build. Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-10-09meson: only build clapi tests when OpenGL is being builtDylan Baker2-2/+2
Otherwise building just vulkan (among other things) will build these tests, pull in a bunch of stuff they shouldn't, and potentially fail to compile. Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-10-09nvc0: fix blitting red to srgb8_alphaIlia Mirkin1-0/+4
For some reason the 2d engine can't handle this. Red formats get special treatment there, so perhaps related. Fixes dEQP-GLES3 tests of the form: dEQP-GLES3.functional.fbo.blit.conversion.r{8,16f,32f}_to_srgb8_alpha8 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Karol Herbst <kherbst@redhat.com> Cc: mesa-stable@lists.freedesktop.org
2018-10-09nv50,nvc0: guard against zero-size blitsIlia Mirkin2-0/+14
The current state tracker can generate these sometimes. Fixing this is more involved, and due to some integer math we can generate divisions-by-zero. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Karol Herbst <kherbst@redhat.com> Cc: mesa-stable@lists.freedesktop.org
2018-10-09nv50,nvc0: mark RGBX_UINT formats as renderableIlia Mirkin1-4/+4
This helps st/mesa avoid some (apparently) buggy fallbacks. Specifically the CopyTexSubImage fallback tries to read texture A as RGBA_FLOAT and write back that data into the target format, which fails for integer formats which have no appropriate logic to do the conversion. Since integer formats don't blend, there's no harm in the fact that the "A" component gets written anyways. Fixes, among others: https://www.khronos.org/registry/webgl/sdk/tests/conformance2/textures/canvas/tex-2d-rgb8ui-rgb_integer-unsigned_byte.html Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: mesa-stable@lists.freedesktop.org
2018-10-09radv: add missing meson c++ visibility argumentsEric Engestrom1-0/+1
Fixes: 6f3aee40f90d725653b6 "radv: using tls to store llvm related info and speed up compiles (v10)" Cc: Dave Airlie <airlied@redhat.com> Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-10-09gbm: Add GBM_FORMAT_ARGB1555 supportMichel Dänzer1-0/+4
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-10-09st/dri: Handle BGRA5551 formatMichel Dänzer1-0/+13
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-10-08freedreno/a5xx+a6xx: fix LRZ pitch alignmentRob Clark1-1/+1
Both RB_2D_DST_SIZE.PITCH (a6xx) and RB_MRT[n].PITCH (a5xx) need alignment to 64. Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-08freedreno/a6xx: add LRZ supportRob Clark8-132/+104
As with a5xx, hidden behind FD_MESA_DEBUG=lrz due to being paranoid about z-fighting issues with some games (in particular, this was observed with 0ad on a5xx.. but I think the proper solution to enable this by default is to figure out how to do driver specific driconf options). Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-08freedreno: update generated headersRob Clark7-38/+120
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-08freedreno/a6xx: add helper for various CP_EVENT_WRITERob Clark5-38/+30
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-08freedreno/a6xx: remove unused fxnsRob Clark2-19/+0
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-08freedreno/a6xx: remove fd6_shader_stateobjRob Clark3-23/+10
Earlier gen's already got this cleanup, but a6xx was still off on a branch then. Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-08glsl: fix array assignments of a swizzled vectorIlia Mirkin1-3/+10
This happens in situations where we might do vec.wzyx[i] = ... The swizzle would get effectively ignored because of the interaction between how ir_assignment->set_lhs works and overwriting the write_mask. There are two cases, one where i is a constant, and another where i is variable. We have to be extra-careful in both cases. Fixes the following WebGL test: https://www.khronos.org/registry/webgl/sdk/tests/conformance2/glsl3/vector-dynamic-indexing-swizzled-lvalue.html And the new piglit tests: swizzled-writemask-indexing-nonconst.shader_test swizzled-writemask-indexing.shader_test Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Cc: mesa-stable@lists.freedesktop.org
2018-10-08radv: tidy up radv_pipeline_init_multisample_state()Samuel Pitoiset1-19/+16
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-08radv: always set PA_SC_MODE_CNTL_1.OUT_OF_ORDER_WATER_MARKSamuel Pitoiset1-2/+2
It has probably no effect without out of order rasterization anyway. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-08radv: set DB_EQAA.INCOHERENT_EQAA_READSSamuel Pitoiset1-1/+1
My attempt was to set this field instead of duplicating one. Fixes: 6cfa321c39 ("radv: add potential missing fields for DB_EQAA") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-10-08i965: fallback RGBX to RGBA in glEGLImageTargetRenderbufferStorageOESChystiakov, Dmytro1-26/+37
In the same fashion as is done for glEGLImageTextureTarget2D. v2: share the fallback which sets baseformat and internalformat correctly which makes both of the tests pass (Tapani) Fixes android.hardware.nativehardware.cts.AHardwareBufferNativeTests: #SingleLayer_ColorTest_GpuColorOutputCpuRead_R8G8B8X8_UNORM #SingleLayer_ColorTest_GpuColorOutputIsRenderable_R8G8B8X8_UNORM Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2018-10-08glsl: do not attempt assignment if operand type not parsed correctlyTapani Pälli1-0/+6
v2: check types of both operands (Ian) Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108012
2018-10-06util/u_queue: add UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITYMarek Olšák4-2/+20
Initial version discussed with Rob Clark under a different patch name. This approach leaves his driver unaffected.
2018-10-06radeonsi: fix a typo at CS_PARTIAL_FLUSHMarek Olšák1-1/+1
harmless
2018-10-06ac: add ac_build_roundMarek Olšák4-6/+20
2018-10-06ac: correct PKT3_COPY_DATA definitionsMarek Olšák7-15/+22
2018-10-06ac: simplify LLVM alloca helpersMarek Olšák1-7/+4
2018-10-06ac: define all address spaces properlyMarek Olšák5-14/+16
2018-10-06gallivm: Make it possible to disable some optimization shortcuts in release ↵Gert Wollny4-21/+32
builds For testing it is of interest that all tests of dEQP pass, e.g. to test virglrenderer on a host only providing software rendering like in a CI. Hence make it possible to disable certain optimizations that make tests fail. While we are there also add some documentation to the flags to make it clear that this is opt-out. Setting the environment variable "GALLIVM_PERF=no_filter_hacks" can be used to make the following tests pass in release mode: dEQP-GLES2.functional.texture.mipmap.2d.affine.*_linear_* dEQP-GLES2.functional.texture.mipmap.cube.generate.* dEQP-GLES2.functional.texture.vertex.2d.filtering.*_mipmap_linear_* dEQP-GLES2.functional.texture.vertex.2d.wrap.* Related: https://bugs.freedesktop.org/show_bug.cgi?id=94957 v2: rename optimization disabling flag to 'safemath' and also move the nopt flag to the perf flags. v3: rename flag "safemath" to "no_filter_hacks" since safemath is usually associated with floating point operations (Roland) Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2018-10-06virgl: Pass resource size and transfer offsetsTomeu Vizoso4-28/+208
Pass the size of a resource when creating it so a backing can be kept in the other side. Also pass the required offset to transfer commands. This moves vtest closer to how virtio-gpu works, making it more useful for testing. v2: - Use new messages for creation and transfers, as changing the behavior of the existing messages would be messy given that we don't want to break compatibility with older servers. v3: - Use correct strides: The resource corresponding to the output display might have a differnt line stride then the IOVs, so when reading back to this resource take the resource stride and the the IOV stride into account. v4: Fix transfer size calculation (Andrey Simiklit) v5: Add comment about transfer size value in the PUT commend (Gurchetan). Add a comment about the size correction for transfers for reading and writing the resource. Fixing this by correctly evaluating the size upfront will need some work also on the virglrenderer side. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> (v2) Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2018-10-06virgl, vtest: Correct the transfer size calculationGert Wollny1-1/+3
The transfer size used in virglrenderer refers to uint32_t, so one must add 3 and then divide by 4 instead of adding 3/4 which is a no-op with integers. Fixes: b3b82fe8ea virgl/vtest: add vtest driver Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2018-10-05util: Make xmlconfig.c build on Solaris without d_type in dirent (v2)Alan Coopersmith1-0/+8
v2: check for lstat() failing Fixes: 04bdbbcab3c "xmlconfig: read more config files from drirc.d/" Signed-off-by: Alan Coopersmith <alan.coopersmith@oracle.com> Reviewed-by: Roland Mainz <roland.mainz@nrubsig.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-10-05radeonsi:optimizing SET_CONTEXT_REG for shaders vgt_vertex_reuseSonny Jiang4-2/+18
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-05radeonsi:optimizing SET_CONTEXT_REG for shaders TessellationSonny Jiang4-5/+26
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-05radeonsi:optimizing SET_CONTEXT_REG for shaders PSSonny Jiang3-14/+60
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-05radeonsi:optimizing SET_CONTEXT_REG for shaders VSSonny Jiang3-33/+77
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-05radeonsi:optimizing SET_CONTEXT_REG for shaders GSSonny Jiang4-24/+154
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-05radeonsi: optimize and allow reg > 31 in radeon_opt_set_context_reg functionsMarek Olšák1-22/+12
reg_saved will have 64 bits, and (1 << reg) where reg > 31 has undefined behavior. (1ull << reg) would be correct for 64 bits. This commit shifts the other way in order to merge the conditions.
2018-10-05radeonsi: optimizing SET_CONTEXT_REG for shaders ESSonny Jiang5-10/+37
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-10-05spirv: mark variables decorated with XfbBuffer as always activeSamuel Pitoiset1-0/+1
Otherwise, they are removed during NIR linking or in some lowering passes. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-10-05docs: update calendar, add news and link release notes to 18.2.2Juan A. Suarez Romero3-7/+8
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
2018-10-05docs: add sha256 checksums for 18.2.2Juan A. Suarez Romero1-1/+2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> (cherry picked from commit cb63a4e1144d9cd8feda3799c68a32a769417b5f)
2018-10-05docs: add release notes for 18.2.2Juan A. Suarez Romero1-0/+154
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> (cherry picked from commit abaeb79eb2c16d7abad06719f24d1e59ad775aa6)
2018-10-04nir/alu_to_scalar: Use ssa_for_alu_src in hand-rolled expansionsJason Ekstrand1-15/+18
The ssa_for_alu_src helper will correctly handle swizzles and other source modifiers for you. The expansions for unpack_half_2x16, pack_uvec2_to_uint, and pack_uvec4_to_uint were all broken with regards to swizzles. The brokenness of unpack_half_2x16 was causing rendering errors in Rise of the Tomb Raider on Intel ever since c11833ab24dcba26 which added an extra copy propagation to the optimization pipeline and caused us to start seeing swizzles where we hadn't seen any before. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107926 Fixes: 9ce901058f3d "nir: Add lowering of nir_op_unpack_half_2x16." Fixes: 9b8786eba955 "nir: Add lowering support for packing opcodes." Tested-by: Alex Smith <asmith@feralinteractive.com> Tested-by: Józef Kucia <joseph.kucia@gmail.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2018-10-04glsl/linker: Check the subroutine associated functions namesVadym Shovkoplias1-0/+40
>From Section 6.1.2 (Subroutines) of the GLSL 4.00 specification "A program will fail to compile or link if any shader or stage contains two or more functions with the same name if the name is associated with a subroutine type." v2: - error out earlier (Tapani) - style fixes (Iago) Fixes: * no-overloads.vert Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108109 Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
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