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| author | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2018-10-03 16:09:24 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2018-10-08 14:17:40 +0200 |
| commit | b38228ccb0e3a0874e8845a325a6b658bc2661ed (patch) | |
| tree | ed4c95444668b4b9af07a2827158bc0424feabf0 | |
| parent | 937986ca1d9a969344e9e85c8afde7ddcc0f1d3a (diff) | |
radv: always set PA_SC_MODE_CNTL_1.OUT_OF_ORDER_WATER_MARK
It has probably no effect without out of order rasterization
anyway.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 6b3e120802e..2db44cb24fd 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -1081,6 +1081,7 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline, ms->pa_sc_mode_cntl_1 = S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) | + S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) | /* always 1: */ S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) | S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) | @@ -1124,8 +1125,7 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline, } if (out_of_order_rast) { - ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) | - S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7); + ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1); } if (vkms && vkms->pSampleMask) { |