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2012-10-09R600: Handle reversed true/false values in selectcctstellar1-6/+8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165528 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09R600: Prefer lowering SELECT_CC to CND* instructions over SET* instructionststellar1-42/+50
SET* instructions are more expensive, because in some cases they require additional instructions to convert their result to the correct type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165527 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09R600: Fix lowering of fcmptstellar1-7/+12
In most cases, R600 requires that all operands of SELECT_CC nodes have the same type. However, we were incorrectly converting between floating point true(1.0f) / false(0.0f) and interger true(-1) / false(0), which was causing miscompiles for fcmp instructions that were lowered to SELECT_CC nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165526 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09R600: Add a pattern for: (selectcc i32, -1, i32, i32, SETGT)tstellar1-0/+7
This is now lowered to a CNDGE_INT instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165525 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09R600: Add a comment explaining why we use TRUNC before FLT_TO_*INTtstellar1-0/+10
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165524 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03SI: Mark the V_CMPX* instructions as having side effectststellar1-0/+32
The side effect is that they write the EXEC register. This prevents them from being dead code eliminated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165155 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03R600: Handle more vector arithmetic instructionststellar1-0/+8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165154 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03R600: Implement getSetCCResultType in R600TargetLowering clasststellar2-0/+8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165153 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03R600: Add support for v4i32 global storeststellar1-0/+6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165152 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03SI: Fix crash in unused register search in LowerFlowControl pasststellar1-4/+4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165115 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03SI: S_WAITCNT has side effectststellar1-0/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165114 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03SI: Set the section in the Asm Printer before emitting program infotstellar1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165113 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03SI: Fix bug in loops where iterators may be deletedtstellar2-2/+4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165112 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02Merge master branchtstellar5-36/+50
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165014 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02R600: improve select_cc lowering to generate CND* more oftentstellar3-42/+88
Patch by: Vincent Lejeune v2: - Simplify isZero() - Remove a unused function prototype - Clean whitespace trails Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165013 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02R600: Fix instruction encoding for r600 family GPUststellar3-15/+15
Tested-by: Michel Dänzer <michel.daenzer@amd.com> https://bugs.freedesktop.org/show_bug.cgi?id=55217 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165012 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02Merge master branchtstellar64-285/+4229
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165011 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02Merge TOTtstellar10-62/+180
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165010 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25R600: Fix typo in R600RegisterInfo.tdtstellar1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164603 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25AMDGPU: Fix register encodingtstellar3-12/+6
The register encodings weren't being defined correctly in the .td files, so they were all encoded as 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164602 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24R600: support for interpolation intrinsicststellar9-1/+307
Patch by Vincent Lejeune. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164538 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24R600: Handle loads from the constants address space.tstellar2-0/+10
Reading from constant memory is not supported yet, so constant reads use global memory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164537 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24R600: Expand vector fadd and fmul on R600tstellar1-0/+3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164536 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24R600: Add support for v4f32 stores on R600tstellar3-9/+27
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164535 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24R600: Add optimization for FP_ROUNDtstellar2-0/+27
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164534 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24R600: Add support for i8 reads on R600tstellar3-0/+25
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164533 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24R600: Replace AMDGPU pow intrinsic with the llvm versiontstellar3-1/+4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164532 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24ARMInstPrinter.cpp: Fix a warning in -Asserts. [-Wunused-variable]tstellar1-0/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164523 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Whitespace.tstellar1-2/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164522 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Fix edge cases of ARM shift operands in arith instructions.tstellar1-38/+6
As before with load instructions, oddities like "asr #32", "rrx" could be printed incorrectly. Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164521 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Fix the handling of edge cases in ARM shifted operands.tstellar4-8/+35
This patch fixes load/store instructions to handle less common cases like "asr #32", "rrx" properly throughout the MC layer. Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164520 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Fix 16-bit atomic inst encoding and keep pseudo-inst starting with '#'tstellar1-14/+14
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164519 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Fix typo in r164357tstellar1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164518 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24MIPS DSP: Add immediate leaves.tstellar1-0/+20
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164513 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24MIPS DSP: Add predicates and instruction template.tstellar1-0/+25
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164512 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Add MIPS DSP register classes. Set actions of DSP vector operations and overridetstellar2-0/+49
TargetLowering's callback functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164511 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24SelectionDAG node enums for MIPS DSP nodes.tstellar2-0/+55
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164510 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Add MIPS accumulator and DSP control registers.tstellar2-1/+45
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164509 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Add flags and feature bits for mips dsp.tstellar2-0/+9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164508 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24[ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser.tstellar4-0/+16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164503 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Add comment.tstellar1-1/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164501 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Add comment.tstellar1-1/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164500 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24[fast-isel] Fallback to SelectionDAG isel if we require strict alignment fortstellar1-0/+6
non-aligned i32 loads/stores. rdar://12304911 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164491 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Some cleanups after merge of Mesa branchtstellar7-468/+7
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164388 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21R600: Emit ISA for ALU instructions in the R600 code emitterMichal Sciubidlo5-148/+249
Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-21R600: Add a fdiv pattern.Tom Stellard1-3/+10
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
2012-09-21R600: reserve also corresponding 128bits regVincent Lejeune1-0/+1
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
2012-09-21R600: Inital flow control support for SITom Stellard6-2/+167
This adds basic flow control support for If-Then-Else blocks using predicates (stored in the EXEC register) and a predicate stack for nested flow control.
2012-09-21R600: Move kernel arg lowering into R600TargetLowering classTom Stellard4-7/+35
2012-09-21R600: Match integer add/sub for SI.Michel Dänzer1-2/+8
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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