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2012-10-09R600: Handle reversed true/false values in selectcctstellar1-6/+8
2012-10-09R600: Prefer lowering SELECT_CC to CND* instructions over SET* instructionststellar1-42/+50
2012-10-09R600: Fix lowering of fcmptstellar1-7/+12
2012-10-09R600: Add a pattern for: (selectcc i32, -1, i32, i32, SETGT)tstellar1-0/+7
2012-10-09R600: Add a comment explaining why we use TRUNC before FLT_TO_*INTtstellar1-0/+10
2012-10-03SI: Mark the V_CMPX* instructions as having side effectststellar1-0/+32
2012-10-03R600: Handle more vector arithmetic instructionststellar1-0/+8
2012-10-03R600: Implement getSetCCResultType in R600TargetLowering clasststellar2-0/+8
2012-10-03R600: Add support for v4i32 global storeststellar1-0/+6
2012-10-03SI: Fix crash in unused register search in LowerFlowControl pasststellar1-4/+4
2012-10-03SI: S_WAITCNT has side effectststellar1-0/+2
2012-10-03SI: Set the section in the Asm Printer before emitting program infotstellar1-1/+1
2012-10-03SI: Fix bug in loops where iterators may be deletedtstellar2-2/+4
2012-10-02Merge master branchtstellar5-36/+50
2012-10-02R600: improve select_cc lowering to generate CND* more oftentstellar3-42/+88
2012-10-02R600: Fix instruction encoding for r600 family GPUststellar3-15/+15
2012-10-02Merge master branchtstellar64-285/+4229
2012-10-02Merge TOTtstellar10-62/+180
2012-09-25R600: Fix typo in R600RegisterInfo.tdtstellar1-1/+1
2012-09-25AMDGPU: Fix register encodingtstellar3-12/+6
2012-09-24R600: support for interpolation intrinsicststellar9-1/+307
2012-09-24R600: Handle loads from the constants address space.tstellar2-0/+10
2012-09-24R600: Expand vector fadd and fmul on R600tstellar1-0/+3
2012-09-24R600: Add support for v4f32 stores on R600tstellar3-9/+27
2012-09-24R600: Add optimization for FP_ROUNDtstellar2-0/+27
2012-09-24R600: Add support for i8 reads on R600tstellar3-0/+25
2012-09-24R600: Replace AMDGPU pow intrinsic with the llvm versiontstellar3-1/+4
2012-09-24ARMInstPrinter.cpp: Fix a warning in -Asserts. [-Wunused-variable]tstellar1-0/+2
2012-09-24Whitespace.tstellar1-2/+2
2012-09-24Fix edge cases of ARM shift operands in arith instructions.tstellar1-38/+6
2012-09-24Fix the handling of edge cases in ARM shifted operands.tstellar4-8/+35
2012-09-24Fix 16-bit atomic inst encoding and keep pseudo-inst starting with '#'tstellar1-14/+14
2012-09-24Fix typo in r164357tstellar1-1/+1
2012-09-24MIPS DSP: Add immediate leaves.tstellar1-0/+20
2012-09-24MIPS DSP: Add predicates and instruction template.tstellar1-0/+25
2012-09-24Add MIPS DSP register classes. Set actions of DSP vector operations and overridetstellar2-0/+49
2012-09-24SelectionDAG node enums for MIPS DSP nodes.tstellar2-0/+55
2012-09-24Add MIPS accumulator and DSP control registers.tstellar2-1/+45
2012-09-24Add flags and feature bits for mips dsp.tstellar2-0/+9
2012-09-24[ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser.tstellar4-0/+16
2012-09-24Add comment.tstellar1-1/+2
2012-09-24Add comment.tstellar1-1/+2
2012-09-24[fast-isel] Fallback to SelectionDAG isel if we require strict alignment fortstellar1-0/+6
2012-09-21Some cleanups after merge of Mesa branchtstellar7-468/+7
2012-09-21R600: Emit ISA for ALU instructions in the R600 code emitterMichal Sciubidlo5-148/+249
2012-09-21R600: Add a fdiv pattern.Tom Stellard1-3/+10
2012-09-21R600: reserve also corresponding 128bits regVincent Lejeune1-0/+1
2012-09-21R600: Inital flow control support for SITom Stellard6-2/+167
2012-09-21R600: Move kernel arg lowering into R600TargetLowering classTom Stellard4-7/+35
2012-09-21R600: Match integer add/sub for SI.Michel Dänzer1-2/+8
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