diff options
| author | tstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8> | 2012-09-24 15:52:49 +0000 |
|---|---|---|
| committer | tstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8> | 2012-09-24 15:52:49 +0000 |
| commit | 21e19fed812339ddd0868fac84c0c2cc6c6f09ac (patch) | |
| tree | 6cf493e70ab4146c9243d7833fbf2c824f901804 /lib/Target | |
| parent | de481a4aa3bb5388783572001598417ea184c03b (diff) | |
R600: Expand vector fadd and fmul on R600
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164536 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/AMDGPU/R600ISelLowering.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/Target/AMDGPU/R600ISelLowering.cpp b/lib/Target/AMDGPU/R600ISelLowering.cpp index 76ce188107..5769f929c3 100644 --- a/lib/Target/AMDGPU/R600ISelLowering.cpp +++ b/lib/Target/AMDGPU/R600ISelLowering.cpp @@ -34,6 +34,9 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) : addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass); computeRegisterProperties(); + setOperationAction(ISD::FADD, MVT::v4f32, Expand); + setOperationAction(ISD::FMUL, MVT::v4f32, Expand); + setOperationAction(ISD::BR_CC, MVT::i32, Custom); setOperationAction(ISD::BR_CC, MVT::f32, Custom); |