~vlj/llvm - AMDGPU backend development for LLVM

Age	Commit message (Expand)	Author	Files	Lines
2012-10-09	R600: Handle reversed true/false values in selectcc	tstellar	1	-6/+8
2012-10-09	R600: Prefer lowering SELECT_CC to CND* instructions over SET* instructions	tstellar	1	-42/+50
2012-10-09	R600: Fix lowering of fcmp	tstellar	1	-7/+12
2012-10-09	R600: Add a pattern for: (selectcc i32, -1, i32, i32, SETGT)	tstellar	1	-0/+7
2012-10-09	R600: Add a comment explaining why we use TRUNC before FLT_TO_*INT	tstellar	1	-0/+10
2012-10-03	SI: Mark the V_CMPX* instructions as having side effects	tstellar	1	-0/+32
2012-10-03	R600: Handle more vector arithmetic instructions	tstellar	1	-0/+8
2012-10-03	R600: Implement getSetCCResultType in R600TargetLowering class	tstellar	2	-0/+8
2012-10-03	R600: Add support for v4i32 global stores	tstellar	1	-0/+6
2012-10-03	SI: Fix crash in unused register search in LowerFlowControl pass	tstellar	1	-4/+4
2012-10-03	SI: S_WAITCNT has side effects	tstellar	1	-0/+2
2012-10-03	SI: Set the section in the Asm Printer before emitting program info	tstellar	1	-1/+1
2012-10-03	SI: Fix bug in loops where iterators may be deleted	tstellar	2	-2/+4
2012-10-02	R600: improve select_cc lowering to generate CND* more often	tstellar	3	-42/+88
2012-10-02	R600: Fix instruction encoding for r600 family GPUs	tstellar	3	-15/+15
2012-09-25	R600: Fix typo in R600RegisterInfo.td	tstellar	1	-1/+1
2012-09-25	AMDGPU: Fix register encoding	tstellar	3	-12/+6
2012-09-24	R600: support for interpolation intrinsics	tstellar	9	-1/+307
2012-09-24	R600: Handle loads from the constants address space.	tstellar	2	-0/+10
2012-09-24	R600: Expand vector fadd and fmul on R600	tstellar	1	-0/+3
2012-09-24	R600: Add support for v4f32 stores on R600	tstellar	3	-9/+27
2012-09-24	R600: Add optimization for FP_ROUND	tstellar	2	-0/+27
2012-09-24	R600: Add support for i8 reads on R600	tstellar	3	-0/+25
2012-09-24	R600: Replace AMDGPU pow intrinsic with the llvm version	tstellar	3	-1/+4
2012-09-21	Some cleanups after merge of Mesa branch	tstellar	7	-468/+7
2012-09-21	R600: Emit ISA for ALU instructions in the R600 code emitter	Michal Sciubidlo	5	-148/+249
2012-09-21	R600: Add a fdiv pattern.	Tom Stellard	1	-3/+10
2012-09-21	R600: reserve also corresponding 128bits reg	Vincent Lejeune	1	-0/+1
2012-09-21	R600: Inital flow control support for SI	Tom Stellard	6	-2/+167
2012-09-21	R600: Move kernel arg lowering into R600TargetLowering class	Tom Stellard	4	-7/+35
2012-09-21	R600: Match integer add/sub for SI.	Michel Dänzer	1	-2/+8
2012-09-21	R600: Complete integer comparison patterns for SI.	Michel Dänzer	1	-4/+12
2012-09-21	R600: Match AMDGPUfract on SI.	Michel Dänzer	1	-1/+3
2012-09-21	R600: Match int_AMDGPU_floor for SI.	Michel Dänzer	1	-1/+3
2012-09-21	R600: Match vector logical operations on SI.	Michel Dänzer	1	-3/+9
2012-09-21	R600: Support frint on SI	Christian König	1	-1/+3
2012-09-21	R600: Fix lowering of vbuild	Tom Stellard	7	-93/+19
2012-09-21	R600: Support fmul on SI	Tom Stellard	1	-1/+4
2012-09-21	R600: Fix operand order of V_CNDMASK in custom inserter	Tom Stellard	1	-1/+1
2012-09-21	R600: Ignore special registers when calculating reg count	Tom Stellard	1	-0/+2
2012-09-21	radeonsi: Handle position input parameter for pixel shaders v2	Tom Stellard	2	-0/+22
2012-09-21	R600: Coding style fixes	Tom Stellard	4	-31/+31
2012-09-21	radeonsi: Move interpolation mode check into the compiler	Tom Stellard	1	-1/+12
2012-09-21	R600: Add SHADER_TYPE instruction	Tom Stellard	8	-1/+32
2012-09-21	R600: Match fexp2 for SI.	Michel Dänzer	1	-1/+3
2012-09-21	AMDGPU: Fix register assembly for SI	Tom Stellard	1	-2/+2
2012-09-21	AMDGPU: Add license to InstPrinter files	Tom Stellard	2	-0/+16
2012-09-21	AMDGPU: Don't print the default predicate state	Tom Stellard	2	-2/+7
2012-09-21	AMDGPU: Fix register names	Tom Stellard	1	-3/+3
2012-09-21	AMDGPU: Use modern tablegen features in *RegisterInfo.td	Tom Stellard	4	-2414/+111