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2013-01-20cover bitcast when explodingcodesizeVincent Lejeune2-0/+10
2013-01-20radeon/llvm: switch instructions matching fmul and int_AMDGPU_mulVincent Lejeune3-7/+8
2013-01-20Initial work to foldVincent Lejeune2-3/+40
2013-01-19R600: improve inputs/interpolation handlingVadim Girlin10-251/+124
2013-01-18R600: add a llvm.R600.store.swizzle intrinsicsVincent Lejeune3-2/+31
2013-01-18R600: simplify stream outputs intrinsicVincent Lejeune5-47/+13
2013-01-18R600: rework handling of the constantsVadim Girlin16-104/+483
2013-01-18R600: Add a CONST_ADDRESS node to model constant buf readVincent Lejeune3-1/+12
2013-01-18R600: Factorise VTX_WORD0 and VTX_WORD1 in tblgen defVincent Lejeune1-45/+65
2013-01-16R600/SI: Use unnormalized coordinates for sampling with the RECT target.Michel Dänzer2-0/+13
2013-01-16R600/SI: Take target parameter for sample intrinsics.Michel Dänzer2-4/+4
2013-01-16R600/SI: Derive all sample intrinsics from a single class.Michel Dänzer1-3/+5
2013-01-08R600: Proper insert S_WAITCNT instructionsChristian König7-32/+378
2013-01-08R600: Optimize and cleanup KILL on SIChristian König4-71/+96
2013-01-04AMDGPU: Rename backend to R600Tom Stellard109-39/+51
2013-01-02DAGCombiner: Avoid generating illegal vector INT_TO_FP nodeststellar4-7/+42
2013-01-02Merge LLVM 3.2 branchTom Stellard190-1855/+6365
2012-12-21R600: Coding style - remove empty spaces from the beginning of functionsTom Stellard3-35/+0
2012-12-21R600: Fix MAX_UINT definitionVadim Girlin1-1/+1
2012-12-21R600: Add SHADOWCUBE to TEX_SHADOW patternVadim Girlin1-1/+1
2012-12-21R600: Expand vec4 INT <-> FP conversionststellar2-0/+56
2012-12-14R600: Remove unecessary VREG alignment.Christian König1-6/+6
2012-12-14R600: control flow optimizationChristian König1-0/+49
2012-12-14R600: New control flow for SI v2Christian König13-384/+1498
2012-12-14R600: enable S_*N2_* instructionsChristian König1-4/+4
2012-12-14R600: BB operand support for SIChristian König4-4/+27
2012-12-14R600: remove nonsense setPrefLoopAlignmentChristian König1-1/+0
2012-12-11R600: Add an intrinsic to handle stream outputs.Vincent Lejeune6-0/+102
2012-12-11R600: Add a field for Export node (compMask) and factorise code handling stor...Vincent Lejeune2-42/+58
2012-12-11R600: Split Word0 and Word1 in Export instructionVincent Lejeune3-49/+60
2012-12-11AMDGPU/SI: Only allow selecting VGPRs with V_CNDMASK_B32.Michel Dänzer1-4/+4
2012-12-11AMDGPU: Match fdiv for SI.Michel Dänzer1-0/+5
2012-12-11R600: Add support for i8 and i16 function argumentsTom Stellard5-15/+92
2012-12-11R600: Improve assembly output for VTX instructionsTom Stellard4-7/+13
2012-12-11AMDGPU: Promote floating-point load/store to integer load/storeTom Stellard4-60/+37
2012-12-11LegalizeDAG: Allow promotion of scalar loadsTom Stellard1-3/+2
2012-12-11LegalizeDAG: Allow type promotion for scalar storesTom Stellard1-3/+4
2012-12-11R600: Convert global store address to dword offset during iselTom Stellard7-14/+46
2012-12-05R600: Fix use iterator in custom select of ISD::ConstantTom Stellard1-2/+3
2012-12-05AMDGPU: add a pattern for min/maxTom Stellard6-8/+79
2012-12-05AMDGPU: replace int_AMDGPU_rcp by fdiv (1.0, x) in RECIP patternVincent Lejeune3-4/+4
2012-12-05AMDGPU: Match AMDGPU.cube intrinsic for SI.Michel Dänzer1-0/+21
2012-12-05AMDGPU: Doxygen fixesTom Stellard72-517/+572
2012-12-05AMDGPU: Various coding style fixesTom Stellard46-518/+452
2012-11-29R600: Fold immediates into ALU instructions when possible v2Tom Stellard9-6/+153
2012-11-29AMDGPU: Remove or document commented out codeTom Stellard4-92/+13
2012-11-29AMDGPU: Fix 4-space indentationTom Stellard3-73/+73
2012-11-29AMDGPU: Remove unused macros v2Tom Stellard6-100/+19
2012-11-29AMDGPU: Coding style - put braces on same line as function headersTom Stellard27-458/+229
2012-11-29AMDGPU: Simplify SI control flow loweringChristian König1-41/+38
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