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authortstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8>2012-09-24 15:52:40 +0000
committertstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8>2012-09-24 15:52:40 +0000
commit2316b7062dfa639f54c197be1a691434f71a1621 (patch)
tree2ade270b755cd515fe4abd03be3249545e26736e /lib/Target/AMDGPU/AMDGPUISelLowering.cpp
parent179cb85cdbb593da6b78a3de2741d9b44a24f38e (diff)
R600: Replace AMDGPU pow intrinsic with the llvm version
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164532 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AMDGPU/AMDGPUISelLowering.cpp')
-rw-r--r--lib/Target/AMDGPU/AMDGPUISelLowering.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 3f9c82076f..d6304a2307 100644
--- a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -34,6 +34,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
// for them.
setOperationAction(ISD::FCEIL, MVT::f32, Legal);
setOperationAction(ISD::FEXP2, MVT::f32, Legal);
+ setOperationAction(ISD::FPOW, MVT::f32, Legal);
setOperationAction(ISD::FRINT, MVT::f32, Legal);
setOperationAction(ISD::UDIV, MVT::i32, Expand);