diff options
| author | tstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8> | 2012-09-24 15:52:40 +0000 |
|---|---|---|
| committer | tstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8> | 2012-09-24 15:52:40 +0000 |
| commit | 2316b7062dfa639f54c197be1a691434f71a1621 (patch) | |
| tree | 2ade270b755cd515fe4abd03be3249545e26736e | |
| parent | 179cb85cdbb593da6b78a3de2741d9b44a24f38e (diff) | |
R600: Replace AMDGPU pow intrinsic with the llvm version
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164532 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/AMDGPU/AMDGPUInstrInfo.td | 2 | ||||
| -rw-r--r-- | lib/Target/AMDGPU/AMDGPUInstructions.td | 2 | ||||
| -rw-r--r-- | test/CodeGen/R600/llvm.pow.ll (renamed from test/CodeGen/R600/llvm.AMDGPU.pow.ll) | 4 |
4 files changed, 6 insertions, 3 deletions
diff --git a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 3f9c82076f..d6304a2307 100644 --- a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -34,6 +34,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : // for them. setOperationAction(ISD::FCEIL, MVT::f32, Legal); setOperationAction(ISD::FEXP2, MVT::f32, Legal); + setOperationAction(ISD::FPOW, MVT::f32, Legal); setOperationAction(ISD::FRINT, MVT::f32, Legal); setOperationAction(ISD::UDIV, MVT::i32, Expand); diff --git a/lib/Target/AMDGPU/AMDGPUInstrInfo.td b/lib/Target/AMDGPU/AMDGPUInstrInfo.td index 4452719686..23ca35aadc 100644 --- a/lib/Target/AMDGPU/AMDGPUInstrInfo.td +++ b/lib/Target/AMDGPU/AMDGPUInstrInfo.td @@ -67,3 +67,5 @@ def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp, // out = (2^32 / a) + e // e is rounding error def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>; + +def fpow : SDNode<"ISD::FPOW", SDTFPBinOp>; diff --git a/lib/Target/AMDGPU/AMDGPUInstructions.td b/lib/Target/AMDGPU/AMDGPUInstructions.td index 3e850ebe18..01948731fb 100644 --- a/lib/Target/AMDGPU/AMDGPUInstructions.td +++ b/lib/Target/AMDGPU/AMDGPUInstructions.td @@ -128,7 +128,7 @@ def SHADER_TYPE : AMDGPUShaderInst < class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul, RegisterClass rc> : Pat < - (int_AMDGPU_pow rc:$src0, rc:$src1), + (fpow rc:$src0, rc:$src1), (exp_ieee (mul rc:$src1, (log_ieee rc:$src0))) >; diff --git a/test/CodeGen/R600/llvm.AMDGPU.pow.ll b/test/CodeGen/R600/llvm.pow.ll index 0e1867a93a..b4ce9f429f 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.pow.ll +++ b/test/CodeGen/R600/llvm.pow.ll @@ -7,7 +7,7 @@ define void @test() { %r0 = call float @llvm.R600.load.input(i32 0) %r1 = call float @llvm.R600.load.input(i32 1) - %r2 = call float @llvm.AMDGPU.pow( float %r0, float %r1) + %r2 = call float @llvm.pow.f32( float %r0, float %r1) call void @llvm.AMDGPU.store.output(float %r2, i32 0) ret void } @@ -16,4 +16,4 @@ declare float @llvm.R600.load.input(i32) readnone declare void @llvm.AMDGPU.store.output(float, i32) -declare float @llvm.AMDGPU.pow(float ,float ) readnone +declare float @llvm.pow.f32(float ,float ) readonly |