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authorVincent Lejeune <vljn@ovi.com>2013-01-20 01:13:44 +0100
committerVincent Lejeune <vljn@ovi.com>2013-01-20 01:13:44 +0100
commit194b03a4f623bc69ada445f079f6ad53db6352e6 (patch)
treea198690111fb8047bfe60589e3ff955ab66ef8a2
parent1d789e072bf8fa662104dea541d0e0b1e7d0d626 (diff)
Initial work to fold
-rw-r--r--lib/Target/R600/AMDILISelDAGToDAG.cpp39
-rw-r--r--lib/Target/R600/R600Instructions.td4
2 files changed, 40 insertions, 3 deletions
diff --git a/lib/Target/R600/AMDILISelDAGToDAG.cpp b/lib/Target/R600/AMDILISelDAGToDAG.cpp
index 567b3e26cf..5b4b88f72a 100644
--- a/lib/Target/R600/AMDILISelDAGToDAG.cpp
+++ b/lib/Target/R600/AMDILISelDAGToDAG.cpp
@@ -23,7 +23,7 @@
#include "llvm/CodeGen/SelectionDAG.h"
#include <list>
#include <queue>
-
+#include <iostream>
using namespace llvm;
//===----------------------------------------------------------------------===//
@@ -171,6 +171,32 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
}
break;
}
+ case ISD::INTRINSIC_WO_CHAIN: {
+ unsigned Intrinsic = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
+ if (Intrinsic == AMDGPUIntrinsic::AMDIL_clamp) {
+ SDNode *SubOperand = NULL;
+ SDNode *PreviousSubOperand;
+ do {
+ PreviousSubOperand = SubOperand;
+ Select(N->getOperand(1).getNode());
+ SubOperand = N->getOperand(1).getNode();
+ } while (PreviousSubOperand != SubOperand);
+ unsigned SubResultOpNum = SubOperand->getNumOperands();
+ const R600InstrInfo *TII =
+ static_cast<const R600InstrInfo*>(TM.getInstrInfo());
+ if (!SubOperand->isMachineOpcode() || !TII->isALUInstr(SubOperand->getMachineOpcode()))
+ return CurDAG->SelectNodeTo(N, AMDGPU::CLAMP_R600, MVT::f32, SDValue(SubOperand,0));
+ unsigned ClampIdx =
+ TII->getOperandIdx(SubOperand->getMachineOpcode(), R600Operands::CLAMP);
+ std::vector<SDValue> Ops;
+ for (unsigned i = 0; i < SubResultOpNum; ++i) {
+ Ops.push_back(SubOperand->getOperand(i));
+ }
+ Ops[ClampIdx - 1] = CurDAG->getTargetConstant(1, MVT::i32);
+ return CurDAG->SelectNodeTo(N, SubOperand->getMachineOpcode(), SubOperand->getVTList(), Ops.data(), SubResultOpNum);
+ }
+ break;
+ }
case ISD::ConstantFP:
case ISD::Constant: {
const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
@@ -303,6 +329,12 @@ bool AMDGPUDAGToDAGISel::FoldOperands(unsigned Opcode,
TII->getOperandIdx(Opcode, R600Operands::SRC1_SEL),
TII->getOperandIdx(Opcode, R600Operands::SRC2_SEL)
};
+ int NegIdx[] = {
+ TII->getOperandIdx(Opcode, R600Operands::SRC0_NEG),
+ TII->getOperandIdx(Opcode, R600Operands::SRC1_NEG),
+ TII->getOperandIdx(Opcode, R600Operands::SRC2_NEG)
+ };
+
for (unsigned i = 0; i < 3; i++) {
if (OperandIdx[i] < 0)
return false;
@@ -318,6 +350,11 @@ bool AMDGPUDAGToDAGISel::FoldOperands(unsigned Opcode,
}
}
break;
+ case ISD::FNEG:
+ Ops[OperandIdx[i] - 1] = Operand.getOperand(0);
+ Ops[NegIdx[i] - 1] = CurDAG->getTargetConstant(1, MVT::i32);
+ return true;
+ break;
default:
break;
}
diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td
index d4709080af..a9aacd9336 100644
--- a/lib/Target/R600/R600Instructions.td
+++ b/lib/Target/R600/R600Instructions.td
@@ -1240,10 +1240,10 @@ let Predicates = [isEGorCayman] in {
// which do not need to be truncated since the fp values are 0.0f or 1.0f.
// We should look into handling these cases separately.
def : Pat<(fp_to_sint R600_Reg32:$src0),
- (FLT_TO_INT_eg (TRUNC R600_Reg32:$src0))>;
+ (FLT_TO_INT_eg R600_Reg32:$src0)>;
def : Pat<(fp_to_uint R600_Reg32:$src0),
- (FLT_TO_UINT_eg (TRUNC R600_Reg32:$src0))>;
+ (FLT_TO_UINT_eg R600_Reg32:$src0)>;
def EG_ExportSwz : ExportSwzInst {
let Word1{19-16} = 1; // BURST_COUNT