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path: root/utils/TableGen/CodeGenSchedule.cpp
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2012-11-13Merge master branchtstellar1-32/+37
Build with clang checkouts: SVN: r167547 Git Mirror: b578aee665aad5ed1a46a26217c730fdfbfc8c2e git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167838 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16Merge master branchtstellar1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166033 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Merge master branchtstellar1-154/+311
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165748 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Machine Model (-schedmodel only). Added SchedAliases.tstellar1-57/+190
Allow subtargets to tie SchedReadWrite types to processor specific sequences or variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164517 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19SchedMachineModel: compress the CPU's WriteLatencyTable.atrick1-0/+15
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164199 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17TableGen subtarget parser: Add getProcResourcesIdx().atrick1-0/+10
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164057 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-15TableGen subtarget parser. Handle new machine model.atrick1-0/+190
Collect processor resources from the subtarget defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163953 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-15TableGen subtarget parser. Handle new machine model.atrick1-0/+495
Infer SchedClasses from variants defined by the target or subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163952 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-15TableGen subtarget parser. Handle new machine model.atrick1-78/+585
Collect SchedClasses and SchedRW types from the subtarget defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163951 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07I'm introducing a new machine model to simultaneously allow simpleAndrew Trick1-0/+151
subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
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