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2013-02-04Tablegen: Revert change that added check for SubRegIndex limitTom Stellard1-5/+2
This was accidently committed in c0f988d7b83f54d87db0ec4052cf06727ff96193
2013-01-29R600: Support for indirect addressing v3Tom Stellard1-2/+5
Only implemented for R600 so far. SI is missing implementations of a few callbacks used by the Indirect Addressing pass and needs code to handle frame indices. At the moment R600 only supports array sizes of 16 dwords or less. Register packing of vector types is currently disabled, which means that a vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order to correctly pack registers in all cases, we will need to implement an analysis pass for R600 that determines the correct vector width for each array. v2: - Add support for i8 zext load from stack. - Coding style fixes v3: - Don't reserve registers for indirect addressing when it isn't being used. - Fix bug caused by LLVM limiting the number of SubRegIndex declarations. XXX: Fixes
2013-01-02Merge LLVM 3.2 branchTom Stellard4-25/+23
2012-11-13Merge master branchtstellar28-367/+1133
Build with clang checkouts: SVN: r167547 Git Mirror: b578aee665aad5ed1a46a26217c730fdfbfc8c2e git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167838 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-22Merge master branchtstellar11-35/+41
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166411 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16Merge master branchtstellar18-146/+147
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166033 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Merge master branchtstellar9-313/+485
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165748 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02Merge master branchtstellar1-48/+49
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165014 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02Merge TOTtstellar1-8/+8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165010 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Machine Model (-schedmodel only). Added SchedAliases.tstellar3-87/+295
Allow subtargets to tie SchedReadWrite types to processor specific sequences or variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164517 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24[ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser.tstellar1-2/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164503 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Whitespace.tstellar1-2/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164497 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Clarify comment.gribozavr1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164371 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19Add in new data types that are used by AMDIL/ANL among others.mvillmow1-0/+8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164261 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19Soften the pattern-can-never-match error in TableGen into a warning. This ↵resistor1-2/+5
pattern can be very useful in cases where you want to define a multiclass that covers both commutative and non-commutative operators (say, add and sub). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164256 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19Remove code for setting the VEX L-bit as a function of operand size from the ↵ctopper2-19/+2
code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164204 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19SchedMachineModel: compress the CPU's WriteLatencyTable.atrick3-7/+44
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164199 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19Iterate deterministicaly over ClassInfo*'ssilvas1-2/+12
Fixes an observed instance of nondeterministic TableGen output. Review by Jakob. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164191 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19Iterate deterministically over register classessilvas1-2/+3
Fixes an observed instance of nondeterministic TableGen output. Review by Jakob. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164190 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19Refactor Record* by-ID comparator to Record.hsilvas2-18/+9
This is a generally useful utility; there's no reason to have it hidden in CodeGenDAGPatterns.cpp. Also, rename it to fit the other comparators in Record.h Review by Jakob. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164189 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18FileCheck: Fix off-by-one bug that made CHECK-NOT: ignore the next character ↵d0k1-2/+2
after the colon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164165 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18Make custom operand parsing mnemonic indices use the same mnemonic table as ↵ctopper1-34/+39
the match table. Reorder fields in OperandMatchEntry to provide the least amount of padding for in tree targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164109 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18Use variable type for index into mnemonic table. Shrinks size of index field ↵ctopper1-5/+14
on in tree targets. Saving static data space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164108 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18Replaced ReInitMCSubtargetInfo with InitMCProcessor.atrick1-1/+2
Now where we used to call ReInitMCSubtargetInfo, we actually recompute the same information as InitMCSubtargetInfo instead of only setting the feature bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164105 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18comment typoatrick1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164097 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18TableGen subtarget emitter. Use getSchedClassIdx.atrick2-11/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164096 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18TableGen subtarget emitter. Generate resolveSchedClass generated hook for ↵atrick1-0/+84
resolving instruction variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164095 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18TableGen subtarget emitter. Remove unnecessary header dependence.atrick1-0/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164094 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵atrick1-6/+25
model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164092 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18Mark asm matcher conversion table as const.ctopper1-5/+5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164088 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18Fix typo in comment. No functional change.ctopper1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164086 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17Backout the wrong subtarget emitter fixatrick1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164078 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17Fix release build after revertingatrick1-2/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164075 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17Revert r164061-r164067. Most of the new subtarget emitter.atrick3-113/+20
I have to work out the Target/CodeGen header dependencies before putting this back. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164072 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17InitMCProcessoratrick1-1/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164066 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17comment typoatrick1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164064 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17TableGen subtarget emitter. Use getSchedClassIdx.atrick2-11/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164063 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17TableGen subtarget emitter. Generate resolveSchedClass generated hook for ↵atrick1-0/+84
resolving instruction variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164062 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵atrick1-7/+25
model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164061 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17TableGen subtarget emitter. Format and emit data tables for the new machine ↵atrick1-6/+117
model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164060 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17TableGen subtarget emitter. Generate data tables for the new machine model.atrick1-2/+291
Map the CodeGenSchedule object model onto data tables. The structure of the data tables is defined in MC, so for convenience we include MCSchedule.h. The alternative is maintaining a redundant copy of the table structure definitions. Mapping the object model onto data tables is sufficiently complicated that it should not be interleaved with emitting source code. This avoids major problem with the backend for itinerary generation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164059 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17TableGen subtarget emitter. Emit processor resources for the new machine model.atrick1-10/+63
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164058 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17TableGen subtarget parser: Add getProcResourcesIdx().atrick1-0/+10
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164057 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17TableGen: Add initializer.grosbach1-1/+1
Keep GCC's warnings happy. It can't reason out that the state machine won't ever hit the potentially uninitialized use in OPC_FilterValue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164041 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17Fix a few vars that can end up being used without initialization.axel1-1/+1
The cases where no initialization happens should still be checked for logic flaws. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164032 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17Fix typohliao1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164012 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-16Add 'virtual' keywoards to output file for overridden functions.ctopper1-5/+6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164002 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-16Add 'virtual' keywoards to output file for overridden functions.ctopper1-7/+7
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163999 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-15Fix Doxygen issues: wrap code examples in \code and use \p to refer togribozavr1-4/+4
parameters. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163984 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-15Revert r163878 as it breaks on targets with alternate register names. Such ↵ctopper2-6/+4
targets do not exist in the main tree so this was not noticed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163959 91177308-0d34-0410-b5e6-96231b3b80d8
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