~sima/drm - danvet's drm/ playground

Age	Commit message (Expand)	Author	Files	Lines
2023-12-15	Merge tag 'mm-hotfixes-stable-2023-12-15-07-11' of git://git.kernel.org/pub/s...	Linus Torvalds	1	-1/+3
2023-12-12	kexec: drop dependency on ARCH_SUPPORTS_KEXEC from CRASH_DUMP	Ignat Korchagin	1	-1/+3
2023-12-06	riscv: Fix SMP when shadow call stacks are enabled	Samuel Holland	1	-1/+1
2023-12-06	riscv: fix misaligned access handling of C.SWSP and C.SDSP	Clément Léger	1	-4/+2
2023-12-06	RISC-V: hwprobe: Always use u64 for extension bits	Andrew Jones	1	-1/+1
2023-12-06	Support rv32 ULEB128 test	Charlie Jenkins	1	-4/+4
2023-12-04	riscv: Correct type casting in module loading	Charlie Jenkins	1	-2/+2
2023-12-04	riscv: Safely remove entries from relocation list	Charlie Jenkins	1	-28/+82
2023-11-10	Merge tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/ker...	Linus Torvalds	40	-336/+1599
2023-11-09	Merge patch "drivers: perf: Do not broadcast to other cpus when starting a co...	Palmer Dabbelt	4	-32/+20
2023-11-08	Merge patch series "Linux RISC-V AIA Preparatory Series"	Palmer Dabbelt	1	-5/+6
2023-11-08	RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs	Anup Patel	1	-5/+6
2023-11-08	Merge tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/ker...	Linus Torvalds	14	-222/+275
2023-11-07	RISC-V: Probe misaligned access speed in parallel	Evan Green	2	-20/+77
2023-11-07	RISC-V: Remove __init on unaligned_emulation_finish()	Evan Green	1	-1/+1
2023-11-07	RISC-V: Show accurate per-hart isa in /proc/cpuinfo	Evan Green	1	-4/+18
2023-11-07	RISC-V: Don't rely on positional structure initialization	Palmer Dabbelt	1	-60/+65
2023-11-07	Merge patch series "riscv: Add remaining module relocations and tests"	Palmer Dabbelt	16	-104/+864
2023-11-07	riscv: Add tests for riscv module loading	Charlie Jenkins	15	-0/+365
2023-11-07	riscv: Add remaining module relocations	Charlie Jenkins	1	-29/+419
2023-11-07	riscv: Avoid unaligned access when relocating modules	Emil Renner Berthing	1	-76/+81
2023-11-06	riscv: kernel: Use correct SYM_DATA_*() macro for data	Clément Léger	1	-5/+4
2023-11-06	riscv: Use SYM_*() assembly macros instead of deprecated ones	Clément Léger	12	-48/+44
2023-11-06	riscv: use ".L" local labels in assembly when applicable	Clément Léger	3	-17/+17
2023-11-06	Merge patch series "riscv: tlb flush improvements"	Palmer Dabbelt	1	-22/+10
2023-11-06	riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb	Alexandre Ghiti	1	-22/+10
2023-11-05	Merge patch series "riscv: vdso.lds.S: some improvement"	Palmer Dabbelt	1	-17/+13
2023-11-05	riscv: vdso.lds.S: remove hardcoded 0x800 .text start addr	Jisheng Zhang	1	-9/+8
2023-11-05	riscv: vdso.lds.S: merge .data section into .rodata section	Jisheng Zhang	1	-8/+7
2023-11-05	riscv: vdso.lds.S: drop __alt_start and __alt_end symbols	Jisheng Zhang	1	-2/+0
2023-11-05	riscv: add userland instruction dump to RISC-V splats	Yunhui Cui	1	-3/+18
2023-11-05	riscv: kprobes: allow writing to x0	Nam Cao	1	-1/+1
2023-11-05	riscv: provide riscv-specific is_trap_insn()	Nam Cao	1	-0/+6
2023-11-05	riscv: don't probe unaligned access speed if already done	Jisheng Zhang	1	-0/+4
2023-11-05	riscv: signal: handle syscall restart before get_signal	Haorong Lu	1	-39/+46
2023-11-05	Merge patch series "Add support to handle misaligned accesses in S-mode"	Palmer Dabbelt	7	-59/+474
2023-11-04	Merge tag 'kbuild-v6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/masa...	Linus Torvalds	2	-20/+0
2023-11-03	Merge tag 'tty-6.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/greg...	Linus Torvalds	2	-12/+2
2023-11-02	Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm	Linus Torvalds	1	-0/+2
2023-11-02	RISC-V: hwprobe: Fix vDSO SIGSEGV	Andrew Jones	1	-1/+1
2023-11-02	Merge patch series "riscv: SCS support"	Palmer Dabbelt	7	-171/+112
2023-11-01	Merge tag 'sysctl-6.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/m...	Linus Torvalds	1	-1/+0
2023-11-01	Merge tag 'docs-6.7' of git://git.lwn.net/linux	Linus Torvalds	1	-1/+1
2023-11-01	riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN	Clément Léger	2	-0/+24
2023-11-01	riscv: report misaligned accesses emulation to hwprobe	Clément Léger	3	-1/+61
2023-11-01	riscv: annotate check_unaligned_access_boot_cpu() with __init	Clément Léger	1	-1/+1
2023-11-01	riscv: add support for sysctl unaligned_enabled control	Clément Léger	1	-0/+9
2023-11-01	riscv: add floating point insn support to misaligned access emulation	Clément Léger	2	-4/+269
2023-11-01	riscv: report perf event for misaligned fault	Clément Léger	1	-0/+5
2023-11-01	riscv: add support for misaligned trap handling in S-mode	Clément Léger	3	-23/+107