diff options
| author | Yang Rong <rong.r.yang@intel.com> | 2014-10-16 15:11:02 +0800 |
|---|---|---|
| committer | Zhigang Gong <zhigang.gong@intel.com> | 2014-10-16 14:45:58 +0800 |
| commit | 9ed3f47ba2fcdaab3988102315a4ab8fee5d3125 (patch) | |
| tree | 5e6f85ff1e635c543460202f1ddc87711768493f /src | |
| parent | bbeac6ee9249e664a33343562d1e8f89b6185c07 (diff) | |
BDW: Also need set Shader Channel Select for constant buffer in BDW.
Signed-off-by: Yang Rong <rong.r.yang@intel.com>
Reviewed-by: Zhigang Gong <zhigang.gong@linux.intel.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/intel/intel_gpgpu.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/intel/intel_gpgpu.c b/src/intel/intel_gpgpu.c index 259882ab..167d8d93 100644 --- a/src/intel/intel_gpgpu.c +++ b/src/intel/intel_gpgpu.c @@ -907,6 +907,12 @@ intel_gpgpu_setup_bti_gen8(intel_gpgpu_t *gpgpu, drm_intel_bo *buf, uint32_t int memset(ss0, 0, sizeof(gen8_surface_state_t)); ss0->ss0.surface_type = I965_SURFACE_BUFFER; ss0->ss0.surface_format = format; + if(format != I965_SURFACEFORMAT_RAW) { + ss0->ss7.shader_channel_select_red = I965_SURCHAN_SELECT_RED; + ss0->ss7.shader_channel_select_green = I965_SURCHAN_SELECT_GREEN; + ss0->ss7.shader_channel_select_blue = I965_SURCHAN_SELECT_BLUE; + ss0->ss7.shader_channel_select_alpha = I965_SURCHAN_SELECT_ALPHA; + } ss0->ss2.width = s & 0x7f; /* bits 6:0 of sz */ assert(ss0->ss2.width & 0x03); ss0->ss2.height = (s >> 7) & 0x3fff; /* bits 20:7 of sz */ |