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| author | Nicolai Hähnle <nicolai.haehnle@amd.com> | 2017-01-16 16:43:54 +0100 |
|---|---|---|
| committer | Nicolai Hähnle <nicolai.haehnle@amd.com> | 2017-01-19 14:51:20 +0100 |
| commit | a207cd99b0ef967161006a1e6c9228a8c7c14d4e (patch) | |
| tree | 8450a77674c5cb1a2d1e60665d91c9b94fff31db | |
| parent | 6895bb0dac1d3b3200b0c89e405e68e122a0ba66 (diff) | |
st/glsl_to_tgsi: use DDIV instead of DRCP + DMULddiv
Fixes GL45-CTS.gpu_shader_fp64.built_in_functions.
v2: use DDIV unconditionally
Reviewed-by: Roland Scheidegger <sroland@vmware.com> (v1)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
| -rw-r--r-- | src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index a99e99178c..d0183d277a 100644 --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp @@ -955,7 +955,7 @@ glsl_to_tgsi_visitor::get_opcode(unsigned op, case3fid(MUL, UMUL, DMUL); case3fid(MAD, UMAD, DMAD); case3fid(FMA, UMAD, DFMA); - case3(DIV, IDIV, UDIV); + case4d(DIV, IDIV, UDIV, DDIV); case4d(MAX, IMAX, UMAX, DMAX); case4d(MIN, IMIN, UMIN, DMIN); case2iu(MOD, UMOD); @@ -1710,10 +1710,7 @@ glsl_to_tgsi_visitor::visit_expression(ir_expression* ir, st_src_reg *op) emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]); break; case ir_binop_div: - if (result_dst.type == GLSL_TYPE_FLOAT || result_dst.type == GLSL_TYPE_DOUBLE) - assert(!"not reached: should be handled by ir_div_to_mul_rcp"); - else - emit_asm(ir, TGSI_OPCODE_DIV, result_dst, op[0], op[1]); + emit_asm(ir, TGSI_OPCODE_DIV, result_dst, op[0], op[1]); break; case ir_binop_mod: if (result_dst.type == GLSL_TYPE_FLOAT) @@ -6918,7 +6915,7 @@ st_link_shader(struct gl_context *ctx, struct gl_shader_program *prog) lower_instructions(ir, MOD_TO_FLOOR | - DIV_TO_MUL_RCP | + FDIV_TO_MUL_RCP | EXP_TO_EXP2 | LOG_TO_LOG2 | LDEXP_TO_ARITH | |