diff options
Diffstat (limited to 'linux/radeon_drv.h')
| -rw-r--r-- | linux/radeon_drv.h | 160 |
1 files changed, 67 insertions, 93 deletions
diff --git a/linux/radeon_drv.h b/linux/radeon_drv.h index 6fb21ca2..2e27398b 100644 --- a/linux/radeon_drv.h +++ b/linux/radeon_drv.h @@ -56,6 +56,7 @@ typedef struct drm_radeon_private { drm_radeon_ring_buffer_t ring; drm_radeon_sarea_t *sarea_priv; + u32 agp_vm_start; int agp_size; int cp_mode; @@ -181,31 +182,6 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new); * for Radeon kernel driver. */ -#if 0 -#define RADEON_AUX_SC_CNTL 0x1660 -# define RADEON_AUX1_SC_EN (1 << 0) -# define RADEON_AUX1_SC_MODE_OR (0 << 1) -# define RADEON_AUX1_SC_MODE_NAND (1 << 1) -# define RADEON_AUX2_SC_EN (1 << 2) -# define RADEON_AUX2_SC_MODE_OR (0 << 3) -# define RADEON_AUX2_SC_MODE_NAND (1 << 3) -# define RADEON_AUX3_SC_EN (1 << 4) -# define RADEON_AUX3_SC_MODE_OR (0 << 5) -# define RADEON_AUX3_SC_MODE_NAND (1 << 5) -#define RADEON_AUX1_SC_LEFT 0x1664 -#define RADEON_AUX1_SC_RIGHT 0x1668 -#define RADEON_AUX1_SC_TOP 0x166c -#define RADEON_AUX1_SC_BOTTOM 0x1670 -#define RADEON_AUX2_SC_LEFT 0x1674 -#define RADEON_AUX2_SC_RIGHT 0x1678 -#define RADEON_AUX2_SC_TOP 0x167c -#define RADEON_AUX2_SC_BOTTOM 0x1680 -#define RADEON_AUX3_SC_LEFT 0x1684 -#define RADEON_AUX3_SC_RIGHT 0x1688 -#define RADEON_AUX3_SC_TOP 0x168c -#define RADEON_AUX3_SC_BOTTOM 0x1690 -#endif - #define RADEON_BUS_CNTL 0x0030 # define RADEON_BUS_MASTER_DIS (1 << 6) @@ -214,11 +190,7 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new); #define RADEON_CLOCK_CNTL_INDEX 0x0008 #define RADEON_CONFIG_APER_SIZE 0x0108 -#if 0 -#define RADEON_CONSTANT_COLOR_C 0x1d34 -#endif -#if 0 #define RADEON_DP_GUI_MASTER_CNTL 0x146c # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) @@ -232,18 +204,10 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new); # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) -# define RADEON_GMC_AUX_CLIP_DIS (1 << 29) # define RADEON_GMC_WR_MSK_DIS (1 << 30) # define RADEON_ROP3_S 0x00cc0000 # define RADEON_ROP3_P 0x00f00000 #define RADEON_DP_WRITE_MASK 0x16cc -#define RADEON_DST_PITCH_OFFSET_C 0x1c80 -#endif - -#if 0 -#define RADEON_GEN_RESET_CNTL 0x00f0 -# define RADEON_SOFT_RESET_GUI (1 << 0) -#endif #define RADEON_GUI_SCRATCH_REG0 0x15e0 #define RADEON_GUI_SCRATCH_REG1 0x15e4 @@ -252,29 +216,28 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new); #define RADEON_GUI_SCRATCH_REG4 0x15f0 #define RADEON_GUI_SCRATCH_REG5 0x15f4 -#if 0 -#define RADEON_GUI_STAT 0x1740 -# define RADEON_GUI_FIFOCNT_MASK 0x0fff -# define RADEON_GUI_ACTIVE (1 << 31) -#endif - #define RADEON_MC_AGP_LOCATION 0x014c #define RADEON_MC_FB_LOCATION 0x0148 #define RADEON_MCLK_CNTL 0x0012 -#if 0 -#define RADEON_PC_GUI_CTLSTAT 0x1748 -#define RADEON_PC_NGUI_CTLSTAT 0x0184 -# define RADEON_PC_FLUSH_GUI (3 << 0) -# define RADEON_PC_RI_GUI (1 << 2) -# define RADEON_PC_FLUSH_ALL 0x00ff -# define RADEON_PC_BUSY (1 << 31) -#define RADEON_PRIM_TEX_CNTL_C 0x1cb0 -#endif +#define RADEON_PP_CNTL 0x1c38 +#define RADEON_PP_LUM_MATRIX 0x1d00 +#define RADEON_PP_MISC 0x1c14 +#define RADEON_PP_ROT_MATRIX_0 0x1d58 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c # define RADEON_RB2D_DC_FLUSH_ALL 0xf # define RADEON_RB2D_DC_BUSY (1 << 31) +#define RADEON_RB3D_CNTL 0x1c3c +# define RADEON_PLANE_MASK_ENABLE (1 << 1) +# define RADEON_Z_ENABLE (1 << 8) +#define RADEON_RB3D_DEPTHOFFSET 0x1c24 +#define RADEON_RB3D_PLANEMASK 0x1d84 +#define RADEON_RB3D_STENCILREFMASK 0x1d7c +#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c +# define RADEON_Z_TEST_MASK (7 << 4) +# define RADEON_Z_TEST_ALWAYS (7 << 4) +# define RADEON_Z_WRITE_ENABLE (1 << 30) #define RADEON_RBBM_SOFT_RESET 0x00f0 # define RADEON_SOFT_RESET_CP (1 << 0) # define RADEON_SOFT_RESET_HI (1 << 1) @@ -287,23 +250,20 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new); #define RADEON_RBBM_STATUS 0x0e40 # define RADEON_RBBM_FIFOCNT_MASK 0x007f # define RADEON_RBBM_ACTIVE (1 << 31) - -#if 0 -#define RADEON_SCALE_3D_CNTL 0x1a00 -#define RADEON_SEC_TEX_CNTL_C 0x1d00 -#define RADEON_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c -#define RADEON_SETUP_CNTL 0x1bc4 -#define RADEON_STEN_REF_MASK_C 0x1d40 -#endif - -#if 0 -#define RADEON_TEX_CNTL_C 0x1c9c -# define RADEON_TEX_CACHE_FLUSH (1 << 23) -#endif - -#if 0 -#define RADEON_WINDOW_XY_OFFSET 0x1bcc -#endif +#define RADEON_RE_LINE_PATTERN 0x1cd0 +#define RADEON_RE_TOP_LEFT 0x26c0 + +#define RADEON_SE_COORD_FMT 0x1c50 +#define RADEON_SE_CNTL 0x1c4c +# define RADEON_BFACE_SOLID (3 << 1) +# define RADEON_BFACE_CULL_MASK (3 << 1) +# define RADEON_FFACE_SOLID (3 << 3) +# define RADEON_FFACE_CULL_MASK (3 << 3) +# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) +# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) +#define RADEON_SE_CNTL_STATUS 0x2140 +#define RADEON_SE_LINE_WIDTH 0x1db8 +#define RADEON_SE_VPORT_XSCALE 0x1d98 /* CP registers */ @@ -322,6 +282,8 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new); # define RADEON_PRE_WRITE_TIMER_SHIFT 0 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23 +#define RADEON_CP_IB_BASE 0x0738 + #define RADEON_CP_CSQ_CNTL 0x0740 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) @@ -334,16 +296,16 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new); #define RADEON_AIC_CNTL 0x01d0 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0) -#if 0 /* CP command packets */ #define RADEON_CP_PACKET0 0x00000000 #define RADEON_CP_PACKET1 0x40000000 #define RADEON_CP_PACKET2 0x80000000 #define RADEON_CP_PACKET3 0xC0000000 +# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 +# define RADEON_3D_DRAW_IMMD 0x00002900 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400 # define RADEON_CNTL_PAINT_MULTI 0x00009A00 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00 -# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 #define RADEON_CP_PACKET_MASK 0xC0000000 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 @@ -351,28 +313,40 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new); #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007 -#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010 -#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020 -#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030 -#define RADEON_CP_VC_CNTL_NUM_SHIFT 16 - -#define RADEON_DATATYPE_CI8 2 -#define RADEON_DATATYPE_ARGB1555 3 -#define RADEON_DATATYPE_RGB565 4 -#define RADEON_DATATYPE_RGB888 5 -#define RADEON_DATATYPE_ARGB8888 6 -#define RADEON_DATATYPE_RGB332 7 -#define RADEON_DATATYPE_RGB8 9 -#define RADEON_DATATYPE_ARGB4444 15 -#endif +#define RADEON_CP_VC_FRMT_XY 0x00000000 +#define RADEON_CP_VC_FRMT_Z 0x80000000 + +#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a +#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010 +#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020 +#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030 +#define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000 +#define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040 +#define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080 +#define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000 +#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100 +#define RADEON_CP_VC_CNTL_NUM_SHIFT 16 + +#define RADEON_COLOR_FORMAT_ARGB1555 3 +#define RADEON_COLOR_FORMAT_RGB565 4 +#define RADEON_COLOR_FORMAT_ARGB8888 6 +#define RADEON_COLOR_FORMAT_RGB332 7 +#define RADEON_COLOR_FORMAT_Y8 8 +#define RADEON_COLOR_FORMAT_RGB8 9 +#define RADEON_COLOR_FORMAT_YUV422_VYUY 11 +#define RADEON_COLOR_FORMAT_YUV422_YVYU 12 +#define RADEON_COLOR_FORMAT_aYUV444 14 +#define RADEON_COLOR_FORMAT_ARGB4444 15 /* Constants */ #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |