diff options
| -rw-r--r-- | linux-core/radeon_drv.c | 2 | ||||
| -rw-r--r-- | linux/agpsupport-pre24.h | 115 | ||||
| -rw-r--r-- | linux/radeon_cp.c | 37 | ||||
| -rw-r--r-- | linux/radeon_drm.h | 172 | ||||
| -rw-r--r-- | linux/radeon_drv.c | 2 | ||||
| -rw-r--r-- | linux/radeon_drv.h | 160 | ||||
| -rw-r--r-- | linux/radeon_state.c | 431 |
7 files changed, 613 insertions, 306 deletions
diff --git a/linux-core/radeon_drv.c b/linux-core/radeon_drv.c index d7440523..9cbb1264 100644 --- a/linux-core/radeon_drv.c +++ b/linux-core/radeon_drv.c @@ -110,7 +110,7 @@ static drm_ioctl_desc_t radeon_ioctls[] = { [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_START)] = { radeon_cp_start, 1, 1 }, [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_STOP)] = { radeon_cp_stop, 1, 1 }, [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_RESET)] = { radeon_cp_reset, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_IDLE)] = { radeon_cp_idle, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_IDLE)] = { radeon_cp_idle, 1, 0 }, [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_SWAP)] = { radeon_cp_swap, 1, 0 }, [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_CLEAR)] = { radeon_cp_clear, 1, 0 }, [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_VERTEX)] = { radeon_cp_vertex, 1, 0 }, diff --git a/linux/agpsupport-pre24.h b/linux/agpsupport-pre24.h new file mode 100644 index 00000000..abcf9f51 --- /dev/null +++ b/linux/agpsupport-pre24.h @@ -0,0 +1,115 @@ +/* agpsupport-pre24.h -- Support for pre-2.4.0 kernels -*- linux-c -*- + * Created: Mon Nov 13 10:54:15 2000 by faith@valinux.com + * + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Author: Rickard E. (Rik) Faith <faith@valinux.com> + * + */ + +#ifndef _AGPSUPPORT_PRE24_H_ +#define _AGPSUPPORT_PRE24_H_ +typedef struct { + void (*free_memory)(agp_memory *); + agp_memory *(*allocate_memory)(size_t, u32); + int (*bind_memory)(agp_memory *, off_t); + int (*unbind_memory)(agp_memory *); + void (*enable)(u32); + int (*acquire)(void); + void (*release)(void); + void (*copy_info)(agp_kern_info *); +} drm_agp_t; + +static drm_agp_t drm_agp_struct = { + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL +}; + +/* The C standard says that 'void *' is not guaranteed to hold a function + pointer, so we use this union to define a generic pointer that is + guaranteed to hold any of the function pointers we care about. */ +typedef union { + void (*free_memory)(agp_memory *); + agp_memory *(*allocate_memory)(size_t, u32); + int (*bind_memory)(agp_memory *, off_t); + int (*unbind_memory)(agp_memory *); + void (*enable)(u32); + int (*acquire)(void); + void (*release)(void); + void (*copy_info)(agp_kern_info *); + unsigned long address; +} drm_agp_func_u; + +typedef struct drm_agp_fill { + const char *name; + drm_agp_func_u *f; +} drm_agp_fill_t; + +static drm_agp_fill_t drm_agp_fill[] = { + { __MODULE_STRING(agp_free_memory), + (drm_agp_func_u *)&drm_agp_struct.free_memory }, + { __MODULE_STRING(agp_allocate_memory), + (drm_agp_func_u *)&drm_agp_struct.allocate_memory }, + { __MODULE_STRING(agp_bind_memory), + (drm_agp_func_u *)&drm_agp_struct.bind_memory }, + { __MODULE_STRING(agp_unbind_memory), + (drm_agp_func_u *)&drm_agp_struct.unbind_memory }, + { __MODULE_STRING(agp_enable), + (drm_agp_func_u *)&drm_agp_struct.enable }, + { __MODULE_STRING(agp_backend_acquire), + (drm_agp_func_u *)&drm_agp_struct.acquire }, + { __MODULE_STRING(agp_backend_release), + (drm_agp_func_u *)&drm_agp_struct.release }, + { __MODULE_STRING(agp_copy_info), + (drm_agp_func_u *)&drm_agp_struct.copy_info }, + { NULL, NULL } +}; + +#define DRM_AGP_GET _drm_agp_get() +#define DRM_AGP_PUT _drm_agp_put() + +static drm_agp_t *_drm_agp_get(void) +{ + drm_agp_fill_t *fill; + int agp_available = 1; + + for (fill = &drm_agp_fill[0]; fill->name; fill++) { + char *n = (char *)fill->name; + *fill->f = (drm_agp_func_u)get_module_symbol(NULL, n); + DRM_DEBUG("%s resolves to 0x%08lx\n", n, (*fill->f).address); + if (!(*fill->f).address) agp_available = 0; + } + return &drm_agp_struct; +} + +static void _drm_agp_put(void) +{ + drm_agp_fill_t *fill; + + for (fill = &drm_agp_fill[0]; fill->name; fill++) { +#if LINUX_VERSION_CODE >= 0x020400 + if ((*fill->f).address) put_module_symbol((*fill->f).address); +#endif + (*fill->f).address = 0; + } +} +#endif diff --git a/linux/radeon_cp.c b/linux/radeon_cp.c index 3dd69ba5..3c31f65d 100644 --- a/linux/radeon_cp.c +++ b/linux/radeon_cp.c @@ -445,30 +445,7 @@ static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv ) */ static int radeon_do_cp_idle( drm_radeon_private_t *dev_priv ) { -#if 1 return radeon_do_wait_for_idle( dev_priv ); -#else - int i; - - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - if ( *dev_priv->ring.head == dev_priv->ring.tail ) { - int pm4stat = RADEON_READ( RADEON_PM4_STAT ); - if ( ( (pm4stat & RADEON_PM4_FIFOCNT_MASK) >= - dev_priv->cp_fifo_size ) && - !(pm4stat & (RADEON_PM4_BUSY | - RADEON_PM4_GUI_ACTIVE)) ) { - return radeon_do_pixcache_flush( dev_priv ); - } - } - udelay( 1 ); - } - -#if 0 - DRM_ERROR( "failed!\n" ); - radeon_status( dev_priv ); -#endif - return -EBUSY; -#endif } /* Start the Concurrent Command Engine. @@ -565,21 +542,20 @@ static int radeon_do_engine_reset( drm_device_t *dev ) static void radeon_cp_init_ring_buffer( drm_device_t *dev ) { drm_radeon_private_t *dev_priv = dev->dev_private; - u32 ring_start, agp_vm_start, cur_read_ptr; + u32 ring_start, cur_read_ptr; u32 tmp; - agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE ); - /* Initialize the memory controller */ RADEON_WRITE( RADEON_MC_FB_LOCATION, - ( agp_vm_start-1 ) & 0xffff0000); + ( dev_priv->agp_vm_start-1 ) & 0xffff0000); RADEON_WRITE( RADEON_MC_AGP_LOCATION, - ( ( ( agp_vm_start-1 + dev_priv->agp_size ) & 0xffff0000) - | ( agp_vm_start >> 16 ) ) ); + ( ( ( dev_priv->agp_vm_start-1 + + dev_priv->agp_size ) & 0xffff0000) + | ( dev_priv->agp_vm_start >> 16 ) ) ); ring_start = dev_priv->cp_ring->offset - dev->agp->base; - RADEON_WRITE( RADEON_CP_RB_BASE, ring_start + agp_vm_start ); + RADEON_WRITE( RADEON_CP_RB_BASE, ring_start + dev_priv->agp_vm_start ); /* Set the write pointer delay */ RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 ); @@ -706,6 +682,7 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) } #endif + dev_priv->agp_vm_start = init->agp_vm_start; dev_priv->agp_size = init->agp_size; dev_priv->ring.head = ((__volatile__ u32 *) diff --git a/linux/radeon_drm.h b/linux/radeon_drm.h index 5066b520..b758660f 100644 --- a/linux/radeon_drm.h +++ b/linux/radeon_drm.h @@ -38,27 +38,31 @@ #ifndef __RADEON_SAREA_DEFINES__ #define __RADEON_SAREA_DEFINES__ -/* What needs to be changed for the current vertex buffer? - */ -#define RADEON_UPLOAD_CONTEXT 0x001 -#define RADEON_UPLOAD_SETUP 0x002 -#define RADEON_UPLOAD_TEX0 0x004 -#define RADEON_UPLOAD_TEX1 0x008 -#define RADEON_UPLOAD_TEX0IMAGES 0x010 -#define RADEON_UPLOAD_TEX1IMAGES 0x020 -#define RADEON_UPLOAD_CORE 0x040 -#define RADEON_UPLOAD_MASKS 0x080 -#define RADEON_UPLOAD_WINDOW 0x100 -#define RADEON_UPLOAD_CLIPRECTS 0x200 /* handled client-side */ -#define RADEON_REQUIRE_QUIESCENCE 0x400 -#define RADEON_UPLOAD_ALL 0x7ff +/* What needs to be changed for the current vertex buffer? */ +#define RADEON_UPLOAD_CONTEXT 0x00000001 +#define RADEON_UPLOAD_VERTFMT 0x00000002 +#define RADEON_UPLOAD_LINE 0x00000004 +#define RADEON_UPLOAD_BUMPMAP 0x00000008 +#define RADEON_UPLOAD_MASKS 0x00000010 +#define RADEON_UPLOAD_VIEWPORT 0x00000020 +#define RADEON_UPLOAD_SETUP 0x00000040 +#define RADEON_UPLOAD_TCL 0x00000080 +#define RADEON_UPLOAD_MISC 0x00000100 +#define RADEON_UPLOAD_TEX0 0x00000200 +#define RADEON_UPLOAD_TEX1 0x00000400 +#define RADEON_UPLOAD_TEX2 0x00000800 +#define RADEON_UPLOAD_TEX0IMAGES 0x00001000 +#define RADEON_UPLOAD_TEX1IMAGES 0x00002000 +#define RADEON_UPLOAD_TEX2IMAGES 0x00004000 +#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ +#define RADEON_REQUIRE_QUIESCENCE 0x00010000 +#define RADEON_UPLOAD_ALL 0x0001ffff #define RADEON_FRONT 0x1 #define RADEON_BACK 0x2 #define RADEON_DEPTH 0x4 -/* Primitive types - */ +/* Primitive types */ #define RADEON_POINTS 0x1 #define RADEON_LINES 0x2 #define RADEON_LINE_STRIP 0x3 @@ -66,29 +70,25 @@ #define RADEON_TRIANGLE_FAN 0x5 #define RADEON_TRIANGLE_STRIP 0x6 -/* Vertex/indirect buffer size - */ +/* Vertex/indirect buffer size */ #if 1 #define RADEON_BUFFER_SIZE 16384 #else #define RADEON_BUFFER_SIZE (128 * 1024) #endif -/* Byte offsets for indirect buffer data - */ +/* Byte offsets for indirect buffer data */ #define RADEON_INDEX_PRIM_OFFSET 20 #define RADEON_HOSTDATA_BLIT_OFFSET 32 -/* 2048x2048 @ 32bpp texture requires this many indirect buffers - */ +/* 2048x2048 @ 32bpp texture requires this many indirect buffers */ #define RADEON_MAX_BLIT_BUFFERS ((2048 * 2048 * 4)/RADEON_BUFFER_SIZE) -/* Keep these small for testing. - */ +/* Keep these small for testing. */ #define RADEON_NR_SAREA_CLIPRECTS 12 /* There are 2 heaps (local/AGP). Each region within a heap is a - * minimum of 64k, and there are at most 64 of them per heap. + * minimum of 64k, and there are at most 64 of them per heap. */ #define RADEON_LOCAL_TEX_HEAP 0 #define RADEON_AGP_TEX_HEAP 1 @@ -102,57 +102,105 @@ #endif /* __RADEON_SAREA_DEFINES__ */ typedef struct { - /* Context state - can be written in one large chunk */ - unsigned int dst_pitch_offset_c; - unsigned int dp_gui_master_cntl_c; - unsigned int sc_top_left_c; - unsigned int sc_bottom_right_c; - unsigned int z_offset_c; - unsigned int z_pitch_c; - unsigned int z_sten_cntl_c; - unsigned int tex_cntl_c; - unsigned int misc_3d_state_cntl_reg; - unsigned int texture_clr_cmp_clr_c; - unsigned int texture_clr_cmp_msk_c; - unsigned int fog_color_c; - - /* Texture state */ - unsigned int tex_size_pitch_c; - unsigned int constant_color_c; + unsigned int red; + unsigned int green; + unsigned int blue; + unsigned int alpha; +} radeon_color_regs_t; - /* Setup state */ - unsigned int pm4_vc_fpu_setup; - unsigned int setup_cntl; +typedef struct { + /* Context state */ + unsigned int pp_misc; /* 0x1c14 */ + unsigned int pp_fog_color; + unsigned int re_solid_color; + unsigned int rb3d_blendcntl; + unsigned int rb3d_depthoffset; + unsigned int rb3d_depthpitch; + unsigned int rb3d_zstencilcntl; + + unsigned int pp_cntl; /* 0x1c38 */ + unsigned int rb3d_cntl; + unsigned int rb3d_coloroffset; + unsigned int re_width_height; + unsigned int rb3d_colorpitch; + unsigned int se_cntl; + + /* Vertex format state */ + unsigned int se_coord_fmt; /* 0x1c50 */ + + /* Line state */ + unsigned int re_line_pattern; /* 0x1cd0 */ + unsigned int re_line_state; + + unsigned int se_line_width; /* 0x1db8 */ + + /* Bumpmap state */ + unsigned int pp_lum_matrix; /* 0x1d00 */ + + unsigned int pp_rot_matrix_0; /* 0x1d58 */ + unsigned int pp_rot_matrix_1; /* Mask state */ - unsigned int dp_write_mask; - unsigned int sten_ref_mask_c; - unsigned int plane_3d_mask_c; + unsigned int rb3d_stencilrefmask; /* 0x1d7c */ + unsigned int rb3d_ropcntl; + unsigned int rb3d_planemask; + + /* Viewport state */ + unsigned int se_vport_xscale; /* 0x1d98 */ + unsigned int se_vport_xoffset; + unsigned int se_vport_yscale; + unsigned int se_vport_yoffset; + unsigned int se_vport_zscale; + unsigned int se_vport_zoffset; - /* Window state */ - unsigned int window_xy_offset; + /* Setup state */ + unsigned int se_cntl_status; /* 0x2140 */ + +#ifdef TCL_ENABLE + /* TCL state */ + radeon_color_regs_t se_tcl_material_emmissive; /* 0x2210 */ + radeon_color_regs_t se_tcl_material_ambient; + radeon_color_regs_t se_tcl_material_diffuse; + radeon_color_regs_t se_tcl_material_specular; + unsigned int se_tcl_shininess; + unsigned int se_tcl_output_vtx_fmt; + unsigned int se_tcl_output_vtx_sel; + unsigned int se_tcl_matrix_select_0; + unsigned int se_tcl_matrix_select_1; + unsigned int se_tcl_ucp_vert_blend_ctl; + unsigned int se_tcl_texture_proc_ctl; + unsigned int se_tcl_light_model_ctl; + unsigned int se_tcl_per_light_ctl[4]; +#endif - /* Core state */ - unsigned int scale_3d_cntl; + /* Misc state */ + unsigned int re_top_left; /* 0x26c0 */ + unsigned int re_misc; } drm_radeon_context_regs_t; /* Setup registers for each texture unit */ typedef struct { - unsigned int tex_cntl; - unsigned int tex_combine_cntl; - unsigned int tex_size_pitch; - unsigned int tex_offset[RADEON_TEX_MAXLEVELS]; - unsigned int tex_border_color; -} drm_radeon_texture_regs_t; + unsigned int pp_txfilter; + unsigned int pp_txformat; + unsigned int pp_txoffset; + unsigned int pp_txcblend; + unsigned int pp_txablend; + unsigned int pp_tfactor; + + unsigned int pp_cubic_faces; + unsigned int pp_border_color; -typedef struct drm_radeon_tex_region { + unsigned int pp_cubic_offset[5]; +} drm_radeon_texture_regs_t; + +typedef struct { unsigned char next, prev; unsigned char in_use; int age; } drm_radeon_tex_region_t; -typedef struct drm_radeon_sarea { +typedef struct { /* The channel for communication of state information to the kernel * on firing a vertex buffer. */ @@ -179,7 +227,7 @@ typedef struct drm_radeon_sarea { /* WARNING: If you change any of these defines, make sure to change the - * defines in the Xserver file (xf86drmRADEON.h) + * defines in the Xserver file (xf86drmRadeon.h) */ typedef struct drm_radeon_init { enum { @@ -209,6 +257,8 @@ typedef struct drm_radeon_init { unsigned int ring_rptr_offset; unsigned int buffers_offset; unsigned int agp_textures_offset; + + unsigned int agp_vm_start; } drm_radeon_init_t; typedef struct drm_radeon_cp_stop { diff --git a/linux/radeon_drv.c b/linux/radeon_drv.c index d7440523..9cbb1264 100644 --- a/linux/radeon_drv.c +++ b/linux/radeon_drv.c @@ -110,7 +110,7 @@ static drm_ioctl_desc_t radeon_ioctls[] = { [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_START)] = { radeon_cp_start, 1, 1 }, [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_STOP)] = { radeon_cp_stop, 1, 1 }, [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_RESET)] = { radeon_cp_reset, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_IDLE)] = { radeon_cp_idle, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_IDLE)] = { radeon_cp_idle, 1, 0 }, [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_SWAP)] = { radeon_cp_swap, 1, 0 }, [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_CLEAR)] = { radeon_cp_clear, 1, 0 }, [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_VERTEX)] = { radeon_cp_vertex, 1, 0 }, diff --git a/linux/radeon_drv.h b/linux/radeon_drv.h index 6fb21ca2..2e27398b 100644 --- a/linux/radeon_drv.h +++ b/linux/radeon_drv.h @@ -56,6 +56,7 @@ typedef struct drm_radeon_private { drm_radeon_ring_buffer_t ring; drm_radeon_sarea_t *sarea_priv; + u32 agp_vm_start; int agp_size; int cp_mode; @@ -181,31 +182,6 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new); * for Radeon kernel driver. */ -#if 0 -#define RADEON_AUX_SC_CNTL 0x1660 -# define RADEON_AUX1_SC_EN (1 << 0) -# define RADEON_AUX1_SC_MODE_OR (0 << 1) -# define RADEON_AUX1_SC_MODE_NAND (1 << 1) -# define RADEON_AUX2_SC_EN (1 << 2) -# define RADEON_AUX2_SC_MODE_OR (0 << 3) -# define RADEON_AUX2_SC_MODE_NAND (1 << 3) -# define RADEON_AUX3_SC_EN (1 << 4) -# define RADEON_AUX3_SC_MODE_OR (0 << 5) -# define RADEON_AUX3_SC_MODE_NAND (1 << 5) -#define RADEON_AUX1_SC_LEFT 0x1664 -#define RADEON_AUX1_SC_RIGHT 0x1668 -#define RADEON_AUX1_SC_TOP 0x166c -#define RADEON_AUX1_SC_BOTTOM 0x1670 -#define RADEON_AUX2_SC_LEFT 0x1674 -#define RADEON_AUX2_SC_RIGHT 0x1678 -#define RADEON_AUX2_SC_TOP 0x167c -#define RADEON_AUX2_SC_BOTTOM 0x1680 -#define RADEON_AUX3_SC_LEFT 0x1684 -#define RADEON_AUX3_SC_RIGHT 0x1688 -#define RADEON_AUX3_SC_TOP 0x168c -#define RADEON_AUX3_SC_BOTTOM 0x1690 -#endif - #define RADEON_BUS_CNTL 0x0030 # define RADEON_BUS_MASTER_DIS (1 << 6) @@ -214,11 +190,7 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new); #define RADEON_CLOCK_CNTL_INDEX 0x0008 #define RADEON_CONFIG_APER_SIZE 0x0108 -#if 0 -#define RADEON_CONSTANT_COLOR_C 0x1d34 -#endif -#if 0 #define RADEON_DP_GUI_MASTER_CNTL 0x146c # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) @@ -232,18 +204,10 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new); # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) -# define RADEON_GMC_AUX_CLIP_DIS (1 << 29) # define RADEON_GMC_WR_MSK_DIS (1 << 30) # define RADEON_ROP3_S 0x00cc0000 # define RADEON_ROP3_P 0x00f00000 #define RADEON_DP_WRITE_MASK 0x16cc -#define RADEON_DST_PITCH_OFFSET_C 0x1c80 -#endif - -#if 0 -#define RADEON_GEN_RESET_CNTL 0x00f0 -# define RADEON_SOFT_RESET_GUI (1 << 0) -#endif #define RADEON_GUI_SCRATCH_REG0 0x15e0 #define RADEON_GUI_SCRATCH_REG1 0x15e4 @@ -252,29 +216,28 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new); #define RADEON_GUI_SCRATCH_REG4 0x15f0 #define RADEON_GUI_SCRATCH_REG5 0x15f4 -#if 0 -#define RADEON_GUI_STAT 0x1740 -# define RADEON_GUI_FIFOCNT_MASK 0x0fff -# define RADEON_GUI_ACTIVE (1 << 31) -#endif - #define RADEON_MC_AGP_LOCATION 0x014c #define RADEON_MC_FB_LOCATION 0x0148 #define RADEON_MCLK_CNTL 0x0012 -#if 0 -#define RADEON_PC_GUI_CTLSTAT 0x1748 -#define RADEON_PC_NGUI_CTLSTAT 0x0184 -# define RADEON_PC_FLUSH_GUI (3 << 0) -# define RADEON_PC_RI_GUI (1 << 2) -# define RADEON_PC_FLUSH_ALL 0x00ff -# define RADEON_PC_BUSY (1 << 31) -#define RADEON_PRIM_TEX_CNTL_C 0x1cb0 -#endif +#define RADEON_PP_CNTL 0x1c38 +#define RADEON_PP_LUM_MATRIX 0x1d00 +#define RADEON_PP_MISC 0x1c14 +#define RADEON_PP_ROT_MATRIX_0 0x1d58 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c # define RADEON_RB2D_DC_FLUSH_ALL 0xf # define RADEON_RB2D_DC_BUSY (1 << 31) +#define RADEON_RB3D_CNTL 0x1c3c +# define RADEON_PLANE_MASK_ENABLE (1 << 1) +# define RADEON_Z_ENABLE (1 << 8) +#define RADEON_RB3D_DEPTHOFFSET 0x1c24 +#define RADEON_RB3D_PLANEMASK 0x1d84 +#define RADEON_RB3D_STENCILREFMASK 0x1d7c +#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c +# define RADEON_Z_TEST_MASK (7 << 4) +# define RADEON_Z_TEST_ALWAYS (7 << 4) +# define RADEON_Z_WRITE_ENABLE (1 << 30) #define RADEON_RBBM_SOFT_RESET 0x00f0 # define RADEON_SOFT_RESET_CP (1 << 0) # define RADEON_SOFT_RESET_HI (1 << 1) @@ -287,23 +250,20 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new); #define RADEON_RBBM_STATUS 0x0e40 # define RADEON_RBBM_FIFOCNT_MASK 0x007f # define RADEON_RBBM_ACTIVE (1 << 31) - -#if 0 -#define RADEON_SCALE_3D_CNTL 0x1a00 -#define RADEON_SEC_TEX_CNTL_C 0x1d00 -#define RADEON_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c -#define RADEON_SETUP_CNTL 0x1bc4 -#define RADEON_STEN_REF_MASK_C 0x1d40 -#endif - -#if 0 -#define RADEON_TEX_CNTL_C 0x1c9c -# define RADEON_TEX_CACHE_FLUSH (1 << 23) -#endif - -#if 0 -#define RADEON_WINDOW_XY_OFFSET 0x1bcc -#endif +#define RADEON_RE_LINE_PATTERN 0x1cd0 +#define RADEON_RE_TOP_LEFT 0x26c0 + +#define RADEON_SE_COORD_FMT 0x1c50 +#define RADEON_SE_CNTL 0x1c4c +# define RADEON_BFACE_SOLID (3 << 1) +# define RADEON_BFACE_CULL_MASK (3 << 1) +# define RADEON_FFACE_SOLID (3 << 3) +# define RADEON_FFACE_CULL_MASK (3 << 3) +# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) +# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) +#define RADEON_SE_CNTL_STATUS 0x2140 +#define RADEON_SE_LINE_WIDTH 0x1db8 +#define RADEON_SE_VPORT_XSCALE 0x1d98 /* CP registers */ @@ -322,6 +282,8 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new); # define RADEON_PRE_WRITE_TIMER_SHIFT 0 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23 +#define RADEON_CP_IB_BASE 0x0738 + #define RADEON_CP_CSQ_CNTL 0x0740 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) @@ -334,16 +296,16 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new); #define RADEON_AIC_CNTL 0x01d0 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0) -#if 0 /* CP command packets */ #define RADEON_CP_PACKET0 0x00000000 #define RADEON_CP_PACKET1 0x40000000 #define RADEON_CP_PACKET2 0x80000000 #define RADEON_CP_PACKET3 0xC0000000 +# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 +# define RADEON_3D_DRAW_IMMD 0x00002900 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400 # define RADEON_CNTL_PAINT_MULTI 0x00009A00 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00 -# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 #define RADEON_CP_PACKET_MASK 0xC0000000 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 @@ -351,28 +313,40 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new); #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007 -#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010 -#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020 -#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030 -#define RADEON_CP_VC_CNTL_NUM_SHIFT 16 - -#define RADEON_DATATYPE_CI8 2 -#define RADEON_DATATYPE_ARGB1555 3 -#define RADEON_DATATYPE_RGB565 4 -#define RADEON_DATATYPE_RGB888 5 -#define RADEON_DATATYPE_ARGB8888 6 -#define RADEON_DATATYPE_RGB332 7 -#define RADEON_DATATYPE_RGB8 9 -#define RADEON_DATATYPE_ARGB4444 15 -#endif +#define RADEON_CP_VC_FRMT_XY 0x00000000 +#define RADEON_CP_VC_FRMT_Z 0x80000000 + +#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a +#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010 +#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020 +#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030 +#define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000 +#define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040 +#define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080 +#define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000 +#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100 +#define RADEON_CP_VC_CNTL_NUM_SHIFT 16 + +#define RADEON_COLOR_FORMAT_ARGB1555 3 +#define RADEON_COLOR_FORMAT_RGB565 4 +#define RADEON_COLOR_FORMAT_ARGB8888 6 +#define RADEON_COLOR_FORMAT_RGB332 7 +#define RADEON_COLOR_FORMAT_Y8 8 +#define RADEON_COLOR_FORMAT_RGB8 9 +#define RADEON_COLOR_FORMAT_YUV422_VYUY 11 +#define RADEON_COLOR_FORMAT_YUV422_YVYU 12 +#define RADEON_COLOR_FORMAT_aYUV444 14 +#define RADEON_COLOR_FORMAT_ARGB4444 15 /* Constants */ #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ diff --git a/linux/radeon_state.c b/linux/radeon_state.c index 0284c4f8..30949ee2 100644 --- a/linux/radeon_state.c +++ b/linux/radeon_state.c @@ -33,6 +33,7 @@ #include "radeon_drv.h" #include "drm.h" +/* This must be defined to 1 for now */ #define USE_OLD_BLITS 1 static drm_radeon_blit_rect_t rects[RADEON_MAX_BLIT_BUFFERS]; @@ -87,9 +88,37 @@ static void radeon_emit_clip_rects( drm_radeon_private_t *dev_priv, #endif } -static inline void radeon_emit_core( drm_radeon_private_t *dev_priv ) +static inline void radeon_emit_context( drm_radeon_private_t *dev_priv ) +{ + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_radeon_context_regs_t *ctx = &sarea_priv->context_state; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 15 ); + + OUT_RING( CP_PACKET0( RADEON_PP_MISC, 6 ) ); + OUT_RING( ctx->pp_misc ); + OUT_RING( ctx->pp_fog_color ); + OUT_RING( ctx->re_solid_color ); + OUT_RING( ctx->rb3d_blendcntl ); + OUT_RING( ctx->rb3d_depthoffset ); + OUT_RING( ctx->rb3d_depthpitch ); + OUT_RING( ctx->rb3d_zstencilcntl ); + + OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 5 ) ); + OUT_RING( ctx->pp_cntl ); + OUT_RING( ctx->rb3d_cntl ); + OUT_RING( ctx->rb3d_coloroffset ); + OUT_RING( ctx->re_width_height ); + OUT_RING( ctx->rb3d_colorpitch ); + OUT_RING( ctx->se_cntl ); + + ADVANCE_RING(); +} + +static inline void radeon_emit_vertfmt( drm_radeon_private_t *dev_priv ) { -#if 0 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_radeon_context_regs_t *ctx = &sarea_priv->context_state; RING_LOCALS; @@ -97,95 +126,175 @@ static inline void radeon_emit_core( drm_radeon_private_t *dev_priv ) BEGIN_RING( 2 ); - OUT_RING( CP_PACKET0( RADEON_SCALE_3D_CNTL, 0 ) ); - OUT_RING( ctx->scale_3d_cntl ); + OUT_RING( CP_PACKET0( RADEON_SE_COORD_FMT, 0 ) ); + OUT_RING( ctx->se_coord_fmt ); ADVANCE_RING(); -#endif } -static inline void radeon_emit_context( drm_radeon_private_t *dev_priv ) +static inline void radeon_emit_line( drm_radeon_private_t *dev_priv ) { -#if 0 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_radeon_context_regs_t *ctx = &sarea_priv->context_state; RING_LOCALS; DRM_DEBUG( " %s\n", __FUNCTION__ ); - BEGIN_RING( 13 ); - - OUT_RING( CP_PACKET0( RADEON_DST_PITCH_OFFSET_C, 11 ) ); - OUT_RING( ctx->dst_pitch_offset_c ); - OUT_RING( ctx->dp_gui_master_cntl_c ); - OUT_RING( ctx->sc_top_left_c ); - OUT_RING( ctx->sc_bottom_right_c ); - OUT_RING( ctx->z_offset_c ); - OUT_RING( ctx->z_pitch_c ); - OUT_RING( ctx->z_sten_cntl_c ); - OUT_RING( ctx->tex_cntl_c ); - OUT_RING( ctx->misc_3d_state_cntl_reg ); - OUT_RING( ctx->texture_clr_cmp_clr_c ); - OUT_RING( ctx->texture_clr_cmp_msk_c ); - OUT_RING( ctx->fog_color_c ); + BEGIN_RING( 5 ); + + OUT_RING( CP_PACKET0( RADEON_RE_LINE_PATTERN, 1 ) ); + OUT_RING( ctx->re_line_pattern ); + OUT_RING( ctx->re_line_state ); + + OUT_RING( CP_PACKET0( RADEON_SE_LINE_WIDTH, 0 ) ); + OUT_RING( ctx->se_line_width ); ADVANCE_RING(); -#endif } -static inline void radeon_emit_setup( drm_radeon_private_t *dev_priv ) +static inline void radeon_emit_bumpmap( drm_radeon_private_t *dev_priv ) { -#if 0 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_radeon_context_regs_t *ctx = &sarea_priv->context_state; RING_LOCALS; DRM_DEBUG( " %s\n", __FUNCTION__ ); - BEGIN_RING( 3 ); + BEGIN_RING( 5 ); - OUT_RING( CP_PACKET1( RADEON_SETUP_CNTL, RADEON_PM4_VC_FPU_SETUP ) ); - OUT_RING( ctx->setup_cntl ); - OUT_RING( ctx->pm4_vc_fpu_setup ); + OUT_RING( CP_PACKET0( RADEON_PP_LUM_MATRIX, 0 ) ); + OUT_RING( ctx->pp_lum_matrix ); + + OUT_RING( CP_PACKET0( RADEON_PP_ROT_MATRIX_0, 1 ) ); + OUT_RING( ctx->pp_rot_matrix_0 ); + OUT_RING( ctx->pp_rot_matrix_1 ); ADVANCE_RING(); -#endif } static inline void radeon_emit_masks( drm_radeon_private_t *dev_priv ) { -#if 0 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_radeon_context_regs_t *ctx = &sarea_priv->context_state; RING_LOCALS; DRM_DEBUG( " %s\n", __FUNCTION__ ); - BEGIN_RING( 5 ); + BEGIN_RING( 4 ); - OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) ); - OUT_RING( ctx->dp_write_mask ); + OUT_RING( CP_PACKET0( RADEON_RB3D_STENCILREFMASK, 2 ) ); + OUT_RING( ctx->rb3d_stencilrefmask ); + OUT_RING( ctx->rb3d_ropcntl ); + OUT_RING( ctx->rb3d_planemask ); - OUT_RING( CP_PACKET0( RADEON_STEN_REF_MASK_C, 1 ) ); - OUT_RING( ctx->sten_ref_mask_c ); - OUT_RING( ctx->plane_3d_mask_c ); + ADVANCE_RING(); +} + +static inline void radeon_emit_viewport( drm_radeon_private_t *dev_priv ) +{ + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_radeon_context_regs_t *ctx = &sarea_priv->context_state; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 7 ); + + OUT_RING( CP_PACKET0( RADEON_SE_VPORT_XSCALE, 5 ) ); + OUT_RING( ctx->se_vport_xscale ); + OUT_RING( ctx->se_vport_xoffset ); + OUT_RING( ctx->se_vport_yscale ); + OUT_RING( ctx->se_vport_yoffset ); + OUT_RING( ctx->se_vport_zscale ); + OUT_RING( ctx->se_vport_zoffset ); ADVANCE_RING(); -#endif } -static inline void radeon_emit_window( drm_radeon_private_t *dev_priv ) +static inline void radeon_emit_setup( drm_radeon_private_t *dev_priv ) { -#if 0 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_radeon_context_regs_t *ctx = &sarea_priv->context_state; RING_LOCALS; DRM_DEBUG( " %s\n", __FUNCTION__ ); - BEGIN_RING( 2 ); + /* Note this duplicates the uploading of se_cntl, which is part + of the context, but adding it here optimizes the reduced + primitive change since we currently render points and lines + with triangles. In the future, we probably won't need this + optimization. */ + +#if 0 + /* Why doesn't CP_PACKET1 work? */ + BEGIN_RING( 3 ); + + OUT_RING( CP_PACKET1( RADEON_SE_CNTL, RADEON_SE_CNTL_STATUS ) ); + OUT_RING( ctx->se_cntl ); + OUT_RING( ctx->se_cntl_status ); +#else + BEGIN_RING( 4 ); + + OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) ); + OUT_RING( ctx->se_cntl ); + OUT_RING( CP_PACKET0( RADEON_SE_CNTL_STATUS, 0 ) ); + OUT_RING( ctx->se_cntl_status ); +#endif + + ADVANCE_RING(); +} + +#ifdef TCL_ENABLE +static inline void radeon_emit_tcl( drm_radeon_private_t *dev_priv ) +{ + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_radeon_context_regs_t *ctx = &sarea_priv->context_state; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); - OUT_RING( CP_PACKET0( RADEON_WINDOW_XY_OFFSET, 0 ) ); - OUT_RING( ctx->window_xy_offset ); + BEGIN_RING( 29 ); + + OUT_RING( CP_PACKET0( RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 27 ) ); + OUT_RING( ctx->se_tcl_material_emmissive.red ); + OUT_RING( ctx->se_tcl_material_emmissive.green ); + OUT_RING( ctx->se_tcl_material_emmissive.blue ); + OUT_RING( ctx->se_tcl_material_emmissive.alpha ); + OUT_RING( ctx->se_tcl_material_ambient.red ); + OUT_RING( ctx->se_tcl_material_ambient.green ); + OUT_RING( ctx->se_tcl_material_ambient.blue ); + OUT_RING( ctx->se_tcl_material_ambient.alpha ); + OUT_RING( ctx->se_tcl_material_diffuse.red ); + OUT_RING( ctx->se_tcl_material_diffuse.green ); + OUT_RING( ctx->se_tcl_material_diffuse.blue ); + OUT_RING( ctx->se_tcl_material_diffuse.alpha ); + OUT_RING( ctx->se_tcl_material_specular.red ); + OUT_RING( ctx->se_tcl_material_specular.green ); + OUT_RING( ctx->se_tcl_material_specular.blue ); + OUT_RING( ctx->se_tcl_material_specular.alpha ); + OUT_RING( ctx->se_tcl_shininess ); + OUT_RING( ctx->se_tcl_output_vtx_fmt ); + OUT_RING( ctx->se_tcl_output_vtx_sel ); + OUT_RING( ctx->se_tcl_matrix_select_0 ); + OUT_RING( ctx->se_tcl_matrix_select_1 ); + OUT_RING( ctx->se_tcl_ucp_vert_blend_ctl ); + OUT_RING( ctx->se_tcl_texture_proc_ctl ); + OUT_RING( ctx->se_tcl_light_model_ctl ); + for (i = 0; i < 4; i++) + OUT_RING( ctx->se_tcl_per_light_ctl[i] ); ADVANCE_RING(); +} #endif + +static inline void radeon_emit_misc( drm_radeon_private_t *dev_priv ) +{ + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_radeon_context_regs_t *ctx = &sarea_priv->context_state; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 3 ); + + OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 1 ) ); + OUT_RING( ctx->re_top_left ); + OUT_RING( ctx->re_misc ); + + ADVANCE_RING(); } static inline void radeon_emit_tex0( drm_radeon_private_t *dev_priv ) @@ -243,6 +352,32 @@ static inline void radeon_emit_tex1( drm_radeon_private_t *dev_priv ) #endif } +static inline void radeon_emit_tex2( drm_radeon_private_t *dev_priv ) +{ +#if 0 + drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[2]; + int i; + RING_LOCALS; + DRM_DEBUG( " %s\n", __FUNCTION__ ); + + BEGIN_RING( 5 + RADEON_TEX_MAXLEVELS ); + + OUT_RING( CP_PACKET0( RADEON_SEC_TEX_CNTL_C, + 1 + RADEON_TEX_MAXLEVELS ) ); + OUT_RING( tex->tex_cntl ); + OUT_RING( tex->tex_combine_cntl ); + for ( i = 0 ; i < RADEON_TEX_MAXLEVELS ; i++ ) { + OUT_RING( tex->tex_offset[i] ); + } + + OUT_RING( CP_PACKET0( RADEON_SEC_TEXTURE_BORDER_COLOR_C, 0 ) ); + OUT_RING( tex->tex_border_color ); + + ADVANCE_RING(); +#endif +} + static inline void radeon_emit_state( drm_radeon_private_t *dev_priv ) { drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -250,19 +385,24 @@ static inline void radeon_emit_state( drm_radeon_private_t *dev_priv ) DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty ); - if ( dirty & RADEON_UPLOAD_CORE ) { - radeon_emit_core( dev_priv ); - sarea_priv->dirty &= ~RADEON_UPLOAD_CORE; - } - if ( dirty & RADEON_UPLOAD_CONTEXT ) { radeon_emit_context( dev_priv ); sarea_priv->dirty &= ~RADEON_UPLOAD_CONTEXT; } - if ( dirty & RADEON_UPLOAD_SETUP ) { - radeon_emit_setup( dev_priv ); - sarea_priv->dirty &= ~RADEON_UPLOAD_SETUP; + if ( dirty & RADEON_UPLOAD_VERTFMT ) { + radeon_emit_vertfmt( dev_priv ); + sarea_priv->dirty &= ~RADEON_UPLOAD_VERTFMT; + } + + if ( dirty & RADEON_UPLOAD_LINE ) { + radeon_emit_line( dev_priv ); + sarea_priv->dirty &= ~RADEON_UPLOAD_LINE; + } + + if ( dirty & RADEON_UPLOAD_BUMPMAP ) { + radeon_emit_bumpmap( dev_priv ); + sarea_priv->dirty &= ~RADEON_UPLOAD_BUMPMAP; } if ( dirty & RADEON_UPLOAD_MASKS ) { @@ -270,9 +410,26 @@ static inline void radeon_emit_state( drm_radeon_private_t *dev_priv ) sarea_priv->dirty &= ~RADEON_UPLOAD_MASKS; } - if ( dirty & RADEON_UPLOAD_WINDOW ) { - radeon_emit_window( dev_priv ); - sarea_priv->dirty &= ~RADEON_UPLOAD_WINDOW; + if ( dirty & RADEON_UPLOAD_VIEWPORT ) { + radeon_emit_viewport( dev_priv ); + sarea_priv->dirty &= ~RADEON_UPLOAD_VIEWPORT; + } + + if ( dirty & RADEON_UPLOAD_SETUP ) { + radeon_emit_setup( dev_priv ); + sarea_priv->dirty &= ~RADEON_UPLOAD_SETUP; + } + +#ifdef TCL_ENABLE + if ( dirty & RADEON_UPLOAD_TCL ) { + radeon_emit_tcl( dev_priv ); + sarea_priv->dirty &= ~RADEON_UPLOAD_TCL; + } +#endif + + if ( dirty & RADEON_UPLOAD_MISC ) { + radeon_emit_misc( dev_priv ); + sarea_priv->dirty &= ~RADEON_UPLOAD_MISC; } if ( dirty & RADEON_UPLOAD_TEX0 ) { @@ -285,6 +442,11 @@ static inline void radeon_emit_state( drm_radeon_private_t *dev_priv ) sarea_priv->dirty &= ~RADEON_UPLOAD_TEX1; } + if ( dirty & RADEON_UPLOAD_TEX2 ) { + radeon_emit_tex1( dev_priv ); + sarea_priv->dirty &= ~RADEON_UPLOAD_TEX1; + } + #if 0 /* Turn off the texture cache flushing */ sarea_priv->context_state.tex_cntl_c &= ~RADEON_TEX_CACHE_FLUSH; @@ -292,6 +454,7 @@ static inline void radeon_emit_state( drm_radeon_private_t *dev_priv ) sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | RADEON_UPLOAD_TEX1IMAGES | + RADEON_UPLOAD_TEX2IMAGES | RADEON_REQUIRE_QUIESCENCE); } @@ -305,7 +468,6 @@ static void radeon_clear_box( drm_radeon_private_t *dev_priv, int x, int y, int w, int h, int r, int g, int b ) { -#if 0 u32 pitch, offset; u32 fb_bpp, color; RING_LOCALS; @@ -317,10 +479,6 @@ static void radeon_clear_box( drm_radeon_private_t *dev_priv, ((g & 0xfc) << 3) | ((b & 0xf8) >> 3)); break; - case 24: - fb_bpp = RADEON_GMC_DST_24BPP; - color = ((r << 16) | (g << 8) | b); - break; case 32: default: fb_bpp = RADEON_GMC_DST_32BPP; @@ -339,17 +497,15 @@ static void radeon_clear_box( drm_radeon_private_t *dev_priv, | fb_bpp | RADEON_GMC_SRC_DATATYPE_COLOR | RADEON_ROP3_P - | RADEON_GMC_CLR_CMP_CNTL_DIS - | RADEON_GMC_AUX_CLIP_DIS ); + | RADEON_GMC_CLR_CMP_CNTL_DIS ); - OUT_RING( (pitch << 21) | (offset >> 5) ); + OUT_RING( (pitch << 22) | (offset >> 5) ); OUT_RING( color ); OUT_RING( (x << 16) | y ); OUT_RING( (w << 16) | h ); ADVANCE_RING(); -#endif } static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv ) @@ -370,16 +526,21 @@ static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv ) static void radeon_print_dirty( const char *msg, unsigned int flags ) { - DRM_DEBUG( "%s: (0x%x) %s%s%s%s%s%s%s%s%s\n", + DRM_DEBUG( "%s: (0x%x) %s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", msg, flags, - (flags & RADEON_UPLOAD_CORE) ? "core, " : "", (flags & RADEON_UPLOAD_CONTEXT) ? "context, " : "", + (flags & RADEON_UPLOAD_VERTFMT) ? "vertfmt, " : "", + (flags & RADEON_UPLOAD_LINE) ? "line, " : "", + (flags & RADEON_UPLOAD_BUMPMAP) ? "bumpmap, " : "", + (flags & RADEON_UPLOAD_MASKS) ? "masks, " : "", + (flags & RADEON_UPLOAD_VIEWPORT) ? "viewport, " : "", (flags & RADEON_UPLOAD_SETUP) ? "setup, " : "", + (flags & RADEON_UPLOAD_TCL) ? "tcl, " : "", + (flags & RADEON_UPLOAD_MISC) ? "misc, " : "", (flags & RADEON_UPLOAD_TEX0) ? "tex0, " : "", (flags & RADEON_UPLOAD_TEX1) ? "tex1, " : "", - (flags & RADEON_UPLOAD_MASKS) ? "masks, " : "", - (flags & RADEON_UPLOAD_WINDOW) ? "window, " : "", + (flags & RADEON_UPLOAD_TEX2) ? "tex2, " : "", (flags & RADEON_UPLOAD_CLIPRECTS) ? "cliprects, " : "", (flags & RADEON_REQUIRE_QUIESCENCE) ? "quiescence, " : "" ); } @@ -392,7 +553,6 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, unsigned int color_mask, unsigned int depth_mask ) { -#if 0 drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; int nbox = sarea_priv->nbox; @@ -408,9 +568,6 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, case 16: fb_bpp = RADEON_GMC_DST_16BPP; break; - case 24: - fb_bpp = RADEON_GMC_DST_24BPP; - break; case 32: default: fb_bpp = RADEON_GMC_DST_32BPP; @@ -420,9 +577,6 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, case 16: depth_bpp = RADEON_GMC_DST_16BPP; break; - case 24: - depth_bpp = RADEON_GMC_DST_32BPP; - break; case 32: depth_bpp = RADEON_GMC_DST_32BPP; break; @@ -463,8 +617,7 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, | fb_bpp | RADEON_GMC_SRC_DATATYPE_COLOR | RADEON_ROP3_P - | RADEON_GMC_CLR_CMP_CNTL_DIS - | RADEON_GMC_AUX_CLIP_DIS ); + | RADEON_GMC_CLR_CMP_CNTL_DIS ); OUT_RING( clear_color ); OUT_RING( (fx << 16) | fy ); OUT_RING( (w << 16) | h ); @@ -485,8 +638,7 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, | fb_bpp | RADEON_GMC_SRC_DATATYPE_COLOR | RADEON_ROP3_P - | RADEON_GMC_CLR_CMP_CNTL_DIS - | RADEON_GMC_AUX_CLIP_DIS ); + | RADEON_GMC_CLR_CMP_CNTL_DIS ); OUT_RING( clear_color ); OUT_RING( (bx << 16) | by ); OUT_RING( (w << 16) | h ); @@ -495,26 +647,84 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, } if ( flags & RADEON_DEPTH ) { - int dx = x + dev_priv->depth_x; - int dy = y + dev_priv->depth_y; + int dx = x; + int dy = y; + drm_radeon_context_regs_t *ctx = + &sarea_priv->context_state; + u32 rb3d_cntl = ctx->rb3d_cntl; + u32 rb3d_zstencilcntl = ctx->rb3d_zstencilcntl; + u32 se_cntl = ctx->se_cntl; DRM_DEBUG( "clear depth: x=%d y=%d\n", dev_priv->depth_x, dev_priv->depth_y ); - BEGIN_RING( 7 ); - OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) ); - OUT_RING( depth_mask ); + rb3d_cntl |= ( RADEON_PLANE_MASK_ENABLE + | RADEON_Z_ENABLE ); + + rb3d_zstencilcntl &= ~RADEON_Z_TEST_MASK; + rb3d_zstencilcntl |= ( RADEON_Z_TEST_ALWAYS + | RADEON_Z_WRITE_ENABLE ); + + se_cntl &= ~( RADEON_VPORT_XY_XFORM_ENABLE + | RADEON_VPORT_Z_XFORM_ENABLE + | RADEON_FFACE_CULL_MASK + | RADEON_BFACE_CULL_MASK ); + se_cntl |= ( RADEON_FFACE_SOLID + | RADEON_BFACE_SOLID ); + + BEGIN_RING( 28 ); + + OUT_RING( CP_PACKET0( RADEON_RB3D_CNTL, 0 ) ); + OUT_RING( rb3d_cntl ); + + OUT_RING( CP_PACKET0( RADEON_RB3D_ZSTENCILCNTL, 0 ) ); + OUT_RING( rb3d_zstencilcntl ); + + OUT_RING( CP_PACKET0( RADEON_RB3D_PLANEMASK, 0 ) ); + OUT_RING( 0x00000000 ); + + OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) ); + OUT_RING( se_cntl ); + + /* Draw rectangle */ + OUT_RING( CP_PACKET3( RADEON_3D_DRAW_IMMD, 10 ) ); + OUT_RING( RADEON_CP_VC_FRMT_XY + | RADEON_CP_VC_FRMT_Z); + OUT_RING( RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE + | RADEON_CP_VC_CNTL_MAOS_ENABLE + | RADEON_CP_VC_CNTL_PRIM_WALK_RING + | RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST + | ( 3 << RADEON_CP_VC_CNTL_NUM_SHIFT ) ); + { + union { + float f; + u32 u; + } val; + + val.f = dx; OUT_RING( val.u ); + val.f = dy; OUT_RING( val.u ); + val.f = clear_depth; OUT_RING( val.u ); + + val.f = dx; OUT_RING( val.u ); + val.f = dy + h; OUT_RING( val.u ); + val.f = clear_depth; OUT_RING( val.u ); + + val.f = dx + w; OUT_RING( val.u ); + val.f = dy + h; OUT_RING( val.u ); + val.f = clear_depth; OUT_RING( val.u ); + } - OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 3 ) ); - OUT_RING( RADEON_GMC_BRUSH_SOLID_COLOR - | depth_bpp - | RADEON_GMC_SRC_DATATYPE_COLOR - | RADEON_ROP3_P - | RADEON_GMC_CLR_CMP_CNTL_DIS - | RADEON_GMC_AUX_CLIP_DIS ); - OUT_RING( clear_depth ); - OUT_RING( (dx << 16) | dy ); - OUT_RING( (w << 16) | h ); + OUT_RING( CP_PACKET0( RADEON_RB3D_CNTL, 0 ) ); + OUT_RING( ctx->rb3d_cntl ); + + OUT_RING( CP_PACKET0( RADEON_RB3D_ZSTENCILCNTL, 0 ) ); + OUT_RING( ctx->rb3d_zstencilcntl ); + + OUT_RING( CP_PACKET0( RADEON_RB3D_PLANEMASK, 0 ) ); + OUT_RING( ctx->rb3d_planemask ); + + OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) ); + OUT_RING( ctx->se_cntl ); ADVANCE_RING(); } @@ -528,8 +738,7 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, | fb_bpp | RADEON_GMC_SRC_DATATYPE_COLOR | RADEON_ROP3_P - | RADEON_GMC_CLR_CMP_CNTL_DIS - | RADEON_GMC_AUX_CLIP_DIS ); + | RADEON_GMC_CLR_CMP_CNTL_DIS ); OUT_RING( ((dev_priv->front_pitch/8) << 21) | (dev_priv->front_offset >> 5) ); @@ -550,8 +759,7 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, | fb_bpp | RADEON_GMC_SRC_DATATYPE_COLOR | RADEON_ROP3_P - | RADEON_GMC_CLR_CMP_CNTL_DIS - | RADEON_GMC_AUX_CLIP_DIS ); + | RADEON_GMC_CLR_CMP_CNTL_DIS ); OUT_RING( ((dev_priv->back_pitch/8) << 21) | (dev_priv->back_offset >> 5) ); @@ -575,8 +783,7 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, | depth_bpp | RADEON_GMC_SRC_DATATYPE_COLOR | RADEON_ROP3_P - | RADEON_GMC_CLR_CMP_CNTL_DIS - | RADEON_GMC_AUX_CLIP_DIS ); + | RADEON_GMC_CLR_CMP_CNTL_DIS ); OUT_RING( ((dev_priv->depth_pitch/8) << 21) | (dev_priv->depth_offset >> 5) ); @@ -589,12 +796,10 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, } #endif } -#endif } static void radeon_cp_dispatch_swap( drm_device_t *dev ) { -#if 0 drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; int nbox = sarea_priv->nbox; @@ -646,7 +851,6 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev ) | fb_bpp | RADEON_ROP3_S | RADEON_GMC_CLR_CMP_CNTL_DIS - | RADEON_GMC_AUX_CLIP_DIS | RADEON_GMC_WR_MSK_DIS ); OUT_RING( (bx << 16) | by ); @@ -666,7 +870,6 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev ) | fb_bpp | RADEON_ROP3_S | RADEON_GMC_CLR_CMP_CNTL_DIS - | RADEON_GMC_AUX_CLIP_DIS | RADEON_GMC_WR_MSK_DIS ); OUT_RING( ((dev_priv->back_pitch/8) << 21) | @@ -694,13 +897,11 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev ) OUT_RING( dev_priv->sarea_priv->last_frame ); ADVANCE_RING(); -#endif } static void radeon_cp_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf ) { -#if 0 drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_buf_priv_t *buf_priv = buf->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -745,7 +946,7 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev, OUT_RING( CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, 3 ) ); - OUT_RING( offset ); + OUT_RING( offset + dev_priv->agp_vm_start ); OUT_RING( size ); OUT_RING( format ); OUT_RING( prim | RADEON_CP_VC_CNTL_PRIM_WALK_LIST | @@ -787,7 +988,6 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev, sarea_priv->dirty &= ~RADEON_UPLOAD_CLIPRECTS; sarea_priv->nbox = 0; -#endif } @@ -797,7 +997,6 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev, drm_buf_t *buf, int start, int end ) { -#if 0 drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_buf_priv_t *buf_priv = buf->dev_private; RING_LOCALS; @@ -842,7 +1041,7 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev, /* Fire off the indirect buffer */ BEGIN_RING( 3 ); - OUT_RING( CP_PACKET0( RADEON_PM4_IW_INDOFF, 1 ) ); + OUT_RING( CP_PACKET0( RADEON_CP_IB_BASE, 1 ) ); OUT_RING( offset ); OUT_RING( dwords ); @@ -875,14 +1074,12 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev, radeon_freelist_reset( dev ); } #endif -#endif } static void radeon_cp_dispatch_indices( drm_device_t *dev, drm_buf_t *buf, int start, int end ) { -#if 0 drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_buf_priv_t *buf_priv = buf->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -922,7 +1119,7 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev, data[0] = CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, dwords-2 ); - data[1] = offset; + data[1] = offset + dev_priv->agp_vm_start; data[2] = RADEON_MAX_VB_VERTS; data[3] = format; data[4] = (prim | RADEON_CP_VC_CNTL_PRIM_WALK_IND | @@ -984,7 +1181,6 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev, sarea_priv->dirty &= ~RADEON_UPLOAD_CLIPRECTS; sarea_priv->nbox = 0; -#endif } static int radeon_cp_dispatch_blit( drm_device_t *dev, @@ -1068,7 +1264,6 @@ static int radeon_cp_dispatch_blit( drm_device_t *dev, | RADEON_ROP3_S | RADEON_DP_SRC_SOURCE_HOST_DATA | RADEON_GMC_CLR_CMP_CNTL_DIS - | RADEON_GMC_AUX_CLIP_DIS | RADEON_GMC_WR_MSK_DIS ); data[2] = (pitch << 21) | (offset >> 5); @@ -1201,13 +1396,11 @@ int radeon_cp_vertex( struct inode *inode, struct file *filp, vertex.idx, dma->buf_count - 1 ); return -EINVAL; } -#if 0 if ( vertex.prim < 0 || - vertex.prim > RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) { + vertex.prim > RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST ) { DRM_ERROR( "buffer prim %d\n", vertex.prim ); return -EINVAL; } -#endif buf = dma->buflist[vertex.idx]; buf_priv = buf->dev_private; @@ -1265,13 +1458,11 @@ int radeon_cp_indices( struct inode *inode, struct file *filp, elts.idx, dma->buf_count - 1 ); return -EINVAL; } -#if 0 if ( elts.prim < 0 || - elts.prim > RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) { + elts.prim > RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST ) { DRM_ERROR( "buffer prim %d\n", elts.prim ); return -EINVAL; } -#endif buf = dma->buflist[elts.idx]; buf_priv = buf->dev_private; |