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path: root/test/CodeGen/R600/trunc.ll
AgeCommit message (Expand)AuthorFilesLines
2015-06-13R600 -> AMDGPU renameTom Stellard1-100/+0
2015-03-23R600/SI: Allow commuting comparesMatt Arsenault1-4/+4
2015-02-27[opaque pointer type] Add textual IR support for explicit type parameter to l...David Blaikie1-2/+2
2015-02-27[opaque pointer type] Add textual IR support for explicit type parameter to g...David Blaikie1-2/+2
2015-02-05R600/SI: Fix i64 truncate to i1Matt Arsenault1-0/+31
2015-01-29R600/SI: Define a schedule model and enable the generic machine schedulerTom Stellard1-0/+2
2015-01-06R600/SI: Add a stub GCNTargetMachineTom Stellard1-1/+1
2014-11-05R600/SI: Change all instruction assembly names to lowercase.Tom Stellard1-18/+18
2014-10-01R600: Call EmitFunctionHeader() in the AsmPrinter to populate the ELF symbol ...Tom Stellard1-6/+6
2014-09-15R600/SI: Prefer selecting more e64 instruction forms.Matt Arsenault1-2/+13
2014-09-11Add DAG combine for shl + add of constants.Matt Arsenault1-3/+3
2014-09-06R600/SI: Fix broken check lines.Matt Arsenault1-3/+3
2014-09-05R600/SI: Use S_ADD_U32 and S_SUB_U32 for low half of 64-bit operationsTom Stellard1-1/+1
2014-08-06R600/SI: Implement areLoadsFromSameBasePtrMatt Arsenault1-4/+5
2014-04-15R600/SI: Print more immediates in hex formatMatt Arsenault1-1/+1
2014-04-03R600/SI: Lower 64-bit immediates using REG_SEQUENCETom Stellard1-2/+3
2014-03-27R600: Implement isZExtFree.Matt Arsenault1-1/+2
2014-03-24R600: Implement isNarrowingProfitable.Matt Arsenault1-5/+18
2014-01-28R600/SI: Add pattern for truncating i32 to i1Michel Danzer1-0/+10
2013-11-13R600/SI: Prefer SALU instructions for bit shift operationsTom Stellard1-1/+2
2013-11-12R600/SI: Change formatting of printed registers.Matt Arsenault1-7/+6
2013-10-23R600: Fix handling of vector kernel argumentsTom Stellard1-1/+0
2013-10-10R600: Fix trunc i64 to i32 on SIMatt Arsenault1-0/+12
2013-10-10R600/SI: Use -verify-machineinstrs for most testsTom Stellard1-1/+1
2013-09-05R600: Fix i64 to i32 trunc on SIMatt Arsenault1-0/+19
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