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AgeCommit message (Expand)AuthorFilesLines
2008-11-18Refactor translation block CPU state handling (Jan Kiszka)aliguori1-0/+8
2008-11-18Convert CPU_PC_FROM_TB to static inline (Jan Kiszka)aliguori1-5/+7
2008-11-17TCG variable type checking.pbrook3-1225/+1212
2008-11-15target-mips: avoid tcg internal error in mfc0/dmfc0aurel321-8/+11
2008-11-11Revert commits 5685 to 5688 committed by mistakeaurel321-0/+4
2008-11-11Don't stop translation for mtc0 compareaurel321-4/+0
2008-11-11target-mips: gen_compute_branch1()aurel321-81/+41
2008-11-11target-mips: optimize movc*()aurel321-48/+33
2008-11-11target-mips: optimize gen_farith()aurel321-12/+12
2008-11-11target-mips: optimize gen_muldiv()aurel321-115/+47
2008-11-11target-mips: optimize gen_arith()/gen_arith_imm()aurel321-46/+32
2008-11-11target-mips: convert bit shuffle ops to TCGaurel323-76/+56
2008-11-11target-mips: convert bitfield ops to TCGaurel323-46/+41
2008-11-11target-mips: optimize gen_op_addr_add() (2/2)aurel323-16/+13
2008-11-11target-mips: optimize gen_op_addr_add() (1/2)aurel321-10/+7
2008-11-11target-mips: optimize gen_save_pc()aurel321-5/+1
2008-11-11target-mips: fix mft* helpers/callaurel323-34/+34
2008-11-11target-mips: fix temporary variable freeing in op_ldst_##insn()aurel321-1/+1
2008-11-04target-mips: use the new rotr/rotri instructionsaurel321-43/+5
2008-10-06Show size for unassigned accesses (Robert Reif)blueswir12-2/+2
2008-09-22Use concet TCG instructions in the MIPS target.ths1-24/+4
2008-09-21Fix Xcontext fill, by Here Poussineau.ths1-1/+1
2008-09-21Add concat_i32_i64 op.pbrook1-17/+6
2008-09-18Use TCG registers for most CPU register accesses.ths1-17/+52
2008-09-18Move the active FPU registers into env again, and use more TCG registersths6-314/+330
2008-09-14MIPS: Fix tlbwi/tlbwraurel321-3/+9
2008-09-14MIPS: remove empty cpu_mips_irqctrl_init()aurel321-1/+0
2008-09-14target-mips: fix warningaurel321-1/+1
2008-09-05TCG fixes for target-mipsaurel321-26/+27
2008-09-02Build fix for gcc-3.3.ths1-0/+4
2008-08-30Fix some warnings that would be generated by gcc -Wredundant-declsblueswir11-3/+0
2008-08-23MIPS: don't free TCG temporary variable twiceaurel321-2/+0
2008-08-01Delete unused variable.ths1-1/+0
2008-07-23Use plain standard inline.ths2-11/+11
2008-07-23Less hardcoding of TARGET_USER_ONLY.ths6-390/+287
2008-07-21A bunch of minor code improvements in the MIPS target.ths2-21/+10
2008-07-21Fix logging output for MIPS HI, LO registers, by Stefan Weil.ths1-1/+2
2008-07-20Fix compiler warning, by Stefan Weil.ths1-1/+1
2008-07-20Simplify conditional FP moves.ths1-10/+5
2008-07-18Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.ths1-7/+5
2008-07-09Use temporary registers for the MIPS FPU emulation.ths5-984/+1849
2008-07-05Fix typo in comment.ths1-1/+1
2008-07-05Change MIPS machine default to Malta.ths1-2/+2
2008-07-01Move interrupt_request and user_mode_only to common cpu state.pbrook1-2/+0
2008-07-01Static'ify some functions, and use standard inline in translate.c.ths1-22/+22
2008-07-01Delete duplicate code.ths1-3/+0
2008-06-30Spelling fixes, spotted by Stuart Brady.ths1-2/+2
2008-06-30Move CPU save/load registration to common code.pbrook1-0/+2
2008-06-30Make bcond and btarget TCG registers.ths1-73/+43
2008-06-29Remove unnecessary helper arguments, and fix some typos.ths3-21/+31
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