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2017-04-14i965/disasm: also print nibctrl in IVB for execsize=8Iago Toral Quiroga1-3/+3
2017-04-14nir: Destination component count of shader_clock intrinsic is 2Boyan Ding2-2/+3
2017-04-14radeonsi: add missing initialization for userptr buffersNicolai Hähnle1-0/+4
2017-04-14radv: remove the temp descriptor set infrastructureFredrik Höglund2-76/+28
2017-04-14radv: use push descriptors in metaFredrik Höglund6-416/+301
2017-04-14radv: add private push descriptors for metaFredrik Höglund2-0/+41
2017-04-14anv/blorp: Properly handle VK_ATTACHMENT_UNUSEDJason Ekstrand1-5/+22
2017-04-14anv/cmd_buffer: Use the null surface state for ATTACHMENT_UNUSEDJason Ekstrand1-2/+14
2017-04-14anv/cmd_buffer: Always set up a null surface stateJason Ekstrand1-31/+19
2017-04-14radeonsi: cope with missing disassemblyNicolai Hähnle1-1/+2
2017-04-14gallium/ddebug: dump missing members of pipe_draw_infoNicolai Hähnle2-0/+7
2017-04-14radeonsi: enable ARB_shader_viewport_layer_arrayNicolai Hähnle1-1/+1
2017-04-14radeonsi: handle ignored LAYER and VIEWPORT_INDEX writesNicolai Hähnle1-0/+20
2017-04-14st/mesa: enable ARB_shader_viewport_layer_arrayNicolai Hähnle1-0/+5
2017-04-14tgsi: clarify TGSI_SEMANTIC_{LAYER,VIEWPORT_INDEX}Nicolai Hähnle1-0/+10
2017-04-14gallium: add PIPE_CAP_TGSI_TES_LAYER_VIEWPORTNicolai Hähnle17-0/+19
2017-04-14anv/cmd_buffer: Flush the VF cache at the top of all primariesJason Ekstrand1-0/+12
2017-04-14anv/blorp: Flush the texture cache in UpdateBufferJason Ekstrand1-0/+7
2017-04-14anv: Limit VkDeviceMemory objects to 2GBJason Ekstrand1-0/+20
2017-04-14intel/blorp: Add a blorp_emit_dynamic macroJason Ekstrand1-64/+50
2017-04-14swr: Enable MSAA in OpenSWR software rendererBruce Cherniak6-25/+313
2017-04-14swr: Removed unnecessary PIPE_BIND flags from swr_is_format_supportedBruce Cherniak1-2/+1
2017-04-14swr: Align swr_context allocation to SIMD alignment.Bruce Cherniak1-2/+5
2017-04-14swr: update gallium driver docsTim Rowley2-6/+12
2017-04-14radv: remove irrelevant commentGrazvydas Ignotas1-1/+1
2017-04-14radv: report timestampPeriod correctlyGrazvydas Ignotas2-2/+2
2017-04-14nir/print: add compute shader infoRob Clark1-0/+13
2017-04-14gallium/docs: small correction about register files for atomicsRob Clark1-2/+4
2017-04-14freedreno: enable draw/batch reordering by defaultRob Clark2-3/+3
2017-04-14freedreno/ir3: small re-orderRob Clark1-24/+23
2017-04-14freedreno/ir3: move 'keeps' to block levelRob Clark5-20/+22
2017-04-14freedreno/ir3: convert dynamic arrays to rallocRob Clark3-14/+8
2017-04-14swr: add linux to scons buildGeorge Kyriazis2-7/+2
2017-04-14radv: make sizes & offsets 32 bit in radv_descriptor_update_template_entry.Bas Nieuwenhuizen2-7/+7
2017-04-13radv: Set descriptor set limits.Bas Nieuwenhuizen1-15/+29
2017-04-13radv: Increase integer sizes in descriptor sets.Bas Nieuwenhuizen1-8/+8
2017-04-14radv: support S8_UINT as a depth/stencil format.Dave Airlie1-1/+1
2017-04-14radv: bump maxGeometryShaderInvocations.Dave Airlie1-1/+1
2017-04-13st/nine: Fix support for ps 1.4 dw and dz modifiersAxel Davy1-2/+2
2017-04-13clover: Add missing include to compat headerJan Vesely1-0/+1
2017-04-13gallium/radeon: never use staging buffers with AMD_pinned_memoryNicolai Hähnle1-2/+16
2017-04-13radeonsi: fix gl_BaseVertex in non-indexed drawsNicolai Hähnle3-4/+23
2017-04-13radeonsi: provide VS_STATE input to all VS variantsNicolai Hähnle5-27/+18
2017-04-13radeonsi: change the bit-packing of LS out/TCS in dataNicolai Hähnle3-9/+14
2017-04-13radeonsi: emit VS_STATE register explicitly from si_draw_vboNicolai Hähnle6-2/+27
2017-04-13radeonsi: extract derived tess state emit to higher levelNicolai Hähnle1-6/+7
2017-04-13radeonsi: drop support for TGSI_SEMANTIC_VERTEXID_NOBASENicolai Hähnle1-2/+3
2017-04-13radv: Add more trace points.Bas Nieuwenhuizen2-0/+3
2017-04-13radv: Ignore CmdUpdateBuffer with size 0.Bas Nieuwenhuizen1-0/+3
2017-04-13radv: Enable query inheritance.Bas Nieuwenhuizen1-1/+1
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