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path: root/src/amd/addrlib
AgeCommit message (Expand)AuthorFilesLines
2017-04-10amd/addrlib: use correct variable name in headerThomas Hindoe Paaboel Andersen1-1/+1
2017-04-04amd/addrlib: second update for Vega10 + bug fixesMarek Olšák17-2132/+3298
2017-04-03amd/addrlib: fix optimized build warningsGrazvydas Ignotas1-1/+1
2017-03-30Partially revert "amd/addrlib: silence warnings" to fix builds with DEBUGMarek Olšák3-6/+6
2017-03-30amd/addrlib: silence warningsMarek Olšák4-15/+15
2017-03-30amd/addrlib: import gfx9 supportNicolai Hähnle16-3/+22032
2017-03-30amd/addrlib: Not all ETC2 formats are 128bpp... add new ETC2 formats to diffe...Kevin Furrow3-19/+45
2017-03-30amd/addrlib: Fix selection of swizzle modes for 3D compressed images.Kevin Furrow1-1/+2
2017-03-30amd/addrlib: Add support for ETC2 and ASTC formats.Kevin Furrow3-1/+119
2017-03-30amd/addrlib: Bump version to 6.02Joe Ma1-1/+1
2017-03-30amd/addrlib: Adjust slie size after pitch and actual height adjustmentFrans Gu1-26/+31
2017-03-30amd/addrlib: Apply input pitch after internal pitch aligningFrans Gu1-12/+33
2017-03-30amdgpu/addrlib: Bump version to 6.01Nicolai Hähnle1-2/+2
2017-03-30amdgpu/addrlib: Seperate 2 dcc related workarounds by different flagsNicolai Hähnle3-3/+9
2017-03-30amdgpu/addrlib: Fix the issue that tcCompatible HTILE slice size is not calcu...Nicolai Hähnle2-0/+18
2017-03-30amdgpu/addrlib: Add a new output flag to notify client that the returned tile...Nicolai Hähnle2-1/+5
2017-03-30amdgpu/addrlib: add matchStencilTileCfg and tcCompatible fixesXavi Zhang4-20/+152
2017-03-30amdgpu/addrlib: Adjust bank equation bit order based on macro tile aspect rat...Frans Gu4-91/+282
2017-03-30amdgpu/addrlib: do some tile mode conversions to display surfaceFrans Gu1-2/+3
2017-03-30amdgpu/addrlib: Check prt flag for PRT_THIN1 extra padding for DCC.Xavi Zhang6-92/+56
2017-03-30amdgpu/addrlib: Add new flags minimizePadding and maxBaseAlignFrans Gu9-157/+401
2017-03-30amdgpu/addrlib: Always returns pixelPitch in original pixelsXavi Zhang1-14/+10
2017-03-30amdgpu/addrlib: fix crash on allocation failureSabre Shao5-36/+31
2017-03-30amdgpu/addrlib: Add flag to report if a surface can have dcc ramFrans Gu3-4/+28
2017-03-30amdgpu/addrlib: support non-power2 height alignment (for linear surface)Roy Zhan1-1/+10
2017-03-30amdgpu/addrlib: Fix family setting for VI and CZ ASICsFrans Gu1-0/+2
2017-03-30amdgpu/addrlib: style cleanupNicolai Hähnle2-28/+15
2017-03-30amdgpu/addrlib: Pad pitch to multiples of 256 for DCC surface on FijiNicolai Hähnle8-49/+131
2017-03-30amdgpu/addrlib: Fix number of //Xavi Zhang8-66/+66
2017-03-30amdgpu/addrlib: Cleanup.Nicolai Hähnle13-73/+68
2017-03-30amdgpu/addrlib: Use namespacesXavi Zhang16-892/+969
2017-03-30amdgpu/addrlib: Adjust 99 "*" to 100 "*" alignmentKevin Zhao18-895/+895
2017-03-30amdgpu/addrlib: Add a new tile mode ADDR_TM_UNKNOWNFrans Gu8-14/+211
2017-03-30amdgpu/addrlib: Stylish cleanup.Xavi Zhang5-17/+16
2017-03-30amdgpu/addrlib: Disable tcComaptible when depth surface is not macro tiledRoy Zhan1-17/+20
2017-03-30amdgpu/addrlib: fix pixel index calculation of thick micro tilingXavi Zhang1-4/+4
2017-03-30amdgpu/addrlib: Add a flag to skip calculate indicesXavi Zhang3-14/+21
2017-03-30amdgpu/addrlib: add equation generationNicolai Hähnle12-118/+1344
2017-03-30amdgpu/addrlib: rename ComputeSurfaceThickness to ThicknessNicolai Hähnle5-32/+32
2017-03-30amdgpu/addrlib: add define HAVE_TSERVERXavi Zhang2-6/+6
2017-03-30amdgpu/addrlib: Add new interface to support macro mode index queryFrans Gu4-0/+115
2017-03-30amdgpu/addrlib: add explicit Log2NonPow2 functionRoy Zhan1-8/+20
2017-03-30amdgpu/addrlib: Fix invalid access to m_tileTableNicolai Hähnle1-6/+17
2017-03-30amdgpu/addrlib: add ADDR_ANALYSIS_ASSUMENicolai Hähnle3-10/+20
2017-03-30amdgpu/addrlib: add tcCompatible htile addr from coordinate support.XiaoYuan Zheng5-13/+80
2017-03-30amdgpu/addrlib: force all zero tile info for linear general.Carlos Xiong1-1/+10
2017-03-30amdgpu/addrlib: Add a member "bpp" for input of method AddrConvertTileIndex a...Nicolai Hähnle7-32/+53
2017-03-30amdgpu/addrlib: Refine the PRT tile mode selectionFrans Gu2-51/+19
2017-03-30amdgpu/addrlib: add dccRamSizeAligned output flagXavi Zhang2-1/+7
2017-03-30amdgpu/addrlib: Change comment alignmentNicolai Hähnle1-12/+12
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