diff options
| author | Samuel Iglesias Gonsálvez <siglesias@igalia.com> | 2016-08-25 16:05:24 +0200 |
|---|---|---|
| committer | Francisco Jerez <currojerez@riseup.net> | 2017-04-14 14:56:08 -0700 |
| commit | a5399e8b1cc3e2e12b8aa067e8380d1b088c35ca (patch) | |
| tree | baf42e6a2b78f06eb592745419f7131969400e83 /src | |
| parent | ebfb703d443a4b22320c3f1eed34e6e1aa54e998 (diff) | |
i965/fs: lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
The hardware applies the same channel enable signals to both halves of
the compressed instruction which will be just wrong under non-uniform
control flow. Fix this by splitting those instructions to SIMD4.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Diffstat (limited to 'src')
| -rw-r--r-- | src/intel/compiler/brw_fs.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index cae15542fa..4dcdc1b46d 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -4598,6 +4598,15 @@ get_fpu_lowered_simd_width(const struct gen_device_info *devinfo, */ if (channels_per_grf != (exec_type_size == 8 ? 4 : 8)) max_width = MIN2(max_width, channels_per_grf); + + /* Lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT + * because HW applies the same channel enable signals to both halves of + * the compressed instruction which will be just wrong under + * non-uniform control flow. + */ + if (devinfo->gen == 7 && !devinfo->is_haswell && + (exec_type_size == 8 || type_sz(inst->dst.type) == 8)) + max_width = MIN2(max_width, 4); } /* Only power-of-two execution sizes are representable in the instruction |