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| author | Andre Maasikas <amaasikas@gmail.com> | 2010-09-21 17:26:06 +0300 |
|---|---|---|
| committer | Andre Maasikas <amaasikas@gmail.com> | 2010-09-21 17:26:06 +0300 |
| commit | afe1c714313242ade0516537dcc2da20bc988d50 (patch) | |
| tree | b382873a8dcff408f192cdc1901d4d2f88ccb377 | |
| parent | 4c0dce3ab3244736cb45a070c4bf2e2ff717cbcf (diff) | |
r600: demo to get shadowtex workingr600-depth
after we rendered to depth texture do a special depth copy
back to texture bo
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_fbo.c | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index 0597d4250d..0ffe6b7cf9 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -546,6 +546,7 @@ radeon_render_texture(GLcontext * ctx, rrb->bo = radeon_image->mt->bo; radeon_bo_ref(rrb->bo); } + radeon_image->mt->tilebits = 1; /* compute offset of the particular 2D image within the texture region */ imageOffset = radeon_miptree_image_offset(radeon_image->mt, @@ -571,7 +572,41 @@ static void radeon_finish_render_texture(GLcontext * ctx, struct gl_renderbuffer_attachment *att) { + radeonContextPtr radeon = RADEON_CONTEXT(ctx); + struct radeon_renderbuffer *rrb = radeon_renderbuffer(att->Renderbuffer); + struct gl_texture_image *texImage = att->Texture->Image[att->CubeMapFace][att->TextureLevel]; + radeon_texture_image * timg = (radeon_texture_image *)texImage; + struct radeon_bo *newbo; + int size = rrb->pitch * rrb->base.Height; + radeon_print(RADEON_TEXTURE, RADEON_TRACE, + "%s(%p, rrb %p, texImage %p, texFormat %s, tiled %d) \n", + __func__, ctx, rrb, texImage, _mesa_get_format_name(texImage->TexFormat),timg->mt->tilebits); + + if(rrb->base.Format == MESA_FORMAT_S8_Z24 && timg->mt->tilebits) { + + newbo = radeon_bo_open(radeon->radeonScreen->bom, + 0, + size, + 0, + RADEON_GEM_DOMAIN_VRAM, + 0); + + radeon->vtbl.blit(ctx, rrb->bo, 0 /*src_offset*/, rrb->base.Format, 0x2 /*ARRAY_1D_TILED_THIN1*/, + rrb->pitch/rrb->cpp, + rrb->pitch/rrb->cpp, rrb->base.Height, 0, 0, /*x,y*/ + newbo, 0 /*dst_offset*/, rrb->base.Format, 0, + rrb->pitch/rrb->cpp, + rrb->pitch/rrb->cpp, timg->base.Height, + 0, 0,/*x,y*/ rrb->pitch/rrb->cpp, rrb->base.Height, 0 /*flip*/); + + timg->mt->bo = newbo; + if (rrb->bo) + radeon_bo_unref(rrb->bo); + rrb->bo = timg->mt->bo; + radeon_bo_ref(rrb->bo); + timg->mt->tilebits=0; + } } static void radeon_validate_framebuffer(GLcontext *ctx, struct gl_framebuffer *fb) |