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authorMax Filippov <jcmvbkbc@gmail.com>2013-07-22 08:02:43 +0400
committerMax Filippov <jcmvbkbc@gmail.com>2017-01-15 13:01:56 -0800
commitd2132510ca88340bed89db5655e65b7cd87d3d8b (patch)
tree374d8cab3c669ef02e54d2483e4f1f4923689950 /target/xtensa/cpu.h
parent59a71f75789fb15bac0a67a18325c4ac1acc981c (diff)
target/xtensa: support icount
Delimit each instruction that may access timers or IRQ state with qemu_io_start/qemu_io_end, so that qemu-system-xtensa could be run with -icount option. Raise EXCP_YIELD after CCOMPARE reprogramming to let tcg_cpu_exec recalculate how long this CPU is allowed to run. RSR now may need to terminate TB, but it can't be done in RSR handler because the same handler is used for XSR together with WSR handler, which may also need to terminate TB. Change RSR and WSR handlers return type to bool indicating whether TB termination is needed (RSR) or has been done (WSR), and add TB termination after RSR/WSR dispatcher call. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa/cpu.h')
-rw-r--r--target/xtensa/cpu.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 744af815aa..a10f1efd8d 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -382,6 +382,7 @@ typedef struct CPUXtensaState {
uint32_t ccount_base;
int exception_taken;
+ int yield_needed;
unsigned static_vectors;
/* Watchpoints for DBREAK registers */
@@ -554,6 +555,7 @@ static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
#define XTENSA_TBFLAG_EXCEPTION 0x4000
#define XTENSA_TBFLAG_WINDOW_MASK 0x18000
#define XTENSA_TBFLAG_WINDOW_SHIFT 15
+#define XTENSA_TBFLAG_YIELD 0x20000
static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
@@ -595,6 +597,9 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
} else {
*flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
}
+ if (env->yield_needed) {
+ *flags |= XTENSA_TBFLAG_YIELD;
+ }
}
#include "exec/cpu-all.h"