diff options
| author | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-08-24 18:32:53 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-09-07 22:25:16 +0200 |
| commit | 8e7291d603a3fa8f0d16feb825629c669f36c49e (patch) | |
| tree | 112714c1acfdc0c1040250c6724266de5ef615c9 /arch/mips/mm | |
| parent | ab5743079b8e3d3d4309664903f6b1f579168a56 (diff) | |
MIPS: Get rid of CAVIUM_OCTEON_DCACHE_PREFETCH_WAR
CAVIUM_OCTEON_DCACHE_PREFETCH_WAR is a check for Octeon model CN6XXXX.
By using the version check we can remove the define.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/mm')
| -rw-r--r-- | arch/mips/mm/uasm.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index c56f129c9a4b..81dd226d6b6b 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -394,7 +394,7 @@ I_u2u1u3(_lddir) void uasm_i_pref(u32 **buf, unsigned int a, signed int b, unsigned int c) { - if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR && a <= 24 && a != 5) + if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && a <= 24 && a != 5) /* * As per erratum Core-14449, replace prefetches 0-4, * 6-24 with 'pref 28'. |