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authorThomas Bogendoerfer <tsbogend@alpha.franken.de>2020-08-24 18:32:53 +0200
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2020-09-07 22:25:16 +0200
commit8e7291d603a3fa8f0d16feb825629c669f36c49e (patch)
tree112714c1acfdc0c1040250c6724266de5ef615c9 /arch/mips
parentab5743079b8e3d3d4309664903f6b1f579168a56 (diff)
MIPS: Get rid of CAVIUM_OCTEON_DCACHE_PREFETCH_WAR
CAVIUM_OCTEON_DCACHE_PREFETCH_WAR is a check for Octeon model CN6XXXX. By using the version check we can remove the define. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/cavium-octeon/setup.c2
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/war.h3
-rw-r--r--arch/mips/mm/uasm.c2
3 files changed, 2 insertions, 5 deletions
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 4f34d92b52f9..8a357cb068c2 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -1126,7 +1126,7 @@ EXPORT_SYMBOL(prom_putchar);
void __init prom_free_prom_memory(void)
{
- if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR) {
+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
/* Check for presence of Core-14449 fix. */
u32 insn;
u32 *foo;
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index 616de70e697c..ba6df0a186e9 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -9,7 +9,4 @@
#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
-#define CAVIUM_OCTEON_DCACHE_PREFETCH_WAR \
- OCTEON_IS_MODEL(OCTEON_CN6XXX)
-
#endif /* __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H */
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index c56f129c9a4b..81dd226d6b6b 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -394,7 +394,7 @@ I_u2u1u3(_lddir)
void uasm_i_pref(u32 **buf, unsigned int a, signed int b,
unsigned int c)
{
- if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR && a <= 24 && a != 5)
+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && a <= 24 && a != 5)
/*
* As per erratum Core-14449, replace prefetches 0-4,
* 6-24 with 'pref 28'.