beignet - Beignet OpenCL Library for Intel Ivy Bridge and newer GPUs (mirrored from https://gitlab.freedesktop.org/beignet/beignet)

Age	Commit message (Expand)	Author	Files	Lines
2016-11-03	Backend: Add subgroup short block read/write	Pan Xiuli	10	-198/+573
2016-11-03	Backend: Add sub groups short shuffle builtin functions	Pan Xiuli	3	-2/+20
2016-11-03	Backend: Add short sub group builtin functions	Pan Xiuli	4	-0/+104
2016-11-03	Backend: Change the sel ir optimization for unpack register	Pan Xiuli	1	-1/+1
2016-11-03	Libocl: Add sub group broadcast short builtin function	Pan Xiuli	2	-0/+13
2016-11-03	Backend: Refine sub group broadcast code for spec	Pan Xiuli	3	-33/+10
2016-11-03	Backend: Refine register offset for simd shuffle	Pan Xiuli	1	-1/+1
2016-11-03	Backend: Refine GenRegiter::offset	Pan Xiuli	1	-0/+4
2016-11-01	GBE: Fix a logical insn with flag bug.	Yang Rong	1	-0/+10
2016-10-27	GBE: Fix assert when get metadata llvm.loop.unroll.enable.	Yang Rong	1	-11/+23
2016-10-21	GBE: fix half immediate negate assert.	Yang Rong	1	-0/+5
2016-10-20	libocl: Provide specs required CL_VERSION macros	Jan Vesely	1	-0/+3
2016-09-28	Backend: Add support for LLVM 3.9 release	Pan Xiuli	11	-30/+272
2016-09-28	Libocl: Image should have access qualifier	Pan Xiuli	2	-205/+355
2016-09-12	Backend: Refine gen ir ALU1 inst getType	Pan Xiuli	2	-13/+9
2016-09-06	GBE: fix uninitialized build warning.	Yang Rong	1	-1/+1
2016-09-05	Libocl: Fix get_sub_group_size bug	Pan Xiuli	1	-2/+2
2016-09-05	Backend: Fix bug for sub/work group functions	Pan Xiuli	2	-14/+14
2016-09-05	Backend: Fix simd shuffle base address	Pan Xiuli	2	-2/+2
2016-09-05	Backend: Fix simd id will broke in simd8 mode	Pan Xiuli	1	-4/+6
2016-08-31	Backend: Refine image block read with less vector and dst tmp	Pan Xiuli	2	-32/+29
2016-08-31	Backend: Resize the selection instruction max dst num	Pan Xiuli	1	-2/+2
2016-08-31	Libocl: Add define for cl_intel_subgroups	Pan Xiuli	1	-0/+1
2016-08-31	Backend: Fix printf bug for simd8	Pan Xiuli	2	-8/+4
2016-08-31	Backend: Refine block_read buffer with unaligned OWord block read	Pan Xiuli	2	-4/+4
2016-08-16	KBL: add kabylake backend support.	Yang Rong	5	-3/+46
2016-08-16	Fix the bug when we pass argument with spaces.	Junyan He	1	-6/+67
2016-08-12	Backend: Add half type for mad	Pan Xiuli	3	-9/+14
2016-08-12	Backend: Add half type support for sub group functions	Pan Xiuli	4	-2/+33
2016-08-12	Libocl: Add half type dot	Pan Xiuli	2	-0/+16
2016-08-12	Libocl: Add vload\store for half type	Pan Xiuli	2	-0/+2
2016-08-03	Backend: Optimization internal math, use mad	Grigore Lupescu	1	-253/+164
2016-08-03	Backend: Optimization internal math, use native	Grigore Lupescu	1	-1/+17
2016-08-03	Backend: Optimization internal math, lower polynomials	Grigore Lupescu	2	-85/+47
2016-08-03	change the bahavior when writing to 3-component vector data types	Guo Yejun	1	-7/+0
2016-07-22	GBE: handle Instrinsic trap and unreachable instruction.	Ruiling Song	1	-1/+3
2016-07-22	GBE: Handle null and uninitialized pointer when do pointer/bti analysis.	Ruiling Song	1	-10/+31
2016-07-20	Backend: Fix image block write bug in simd8	Pan Xiuli	1	-1/+1
2016-07-20	Backend: Add intel_sub_group_shuffle_down/up/xor with shuffle	Pan Xiuli	3	-0/+52
2016-07-20	Backend: Add gen8+ instruction compact support	Pan Xiuli	6	-69/+403
2016-07-20	Backend: Change disable compact to compact version	Pan Xiuli	3	-4/+4
2016-07-20	GBE: handle mad with execution width of one.	Ruiling Song	1	-2/+12
2016-07-15	Backend: Refine sel ir optimization	Pan Xiuli	1	-6/+11
2016-07-15	Backend: Add missing math function control code for gen8+	Pan Xiuli	1	-0/+2
2016-07-13	Report build failures in backend to the build log	Rebecca N. Palmer	4	-14/+59
2016-07-04	GBE: reorder the condition to avoid array overflow.	Yang Rong	1	-1/+1
2016-06-24	Backend: Refine block read image	Pan Xiuli	2	-11/+22
2016-06-24	Backend: Refine block read/write buffer	Pan Xiuli	7	-87/+264
2016-06-24	GBE: Improve spill policy by considering use count.	Ruiling Song	6	-114/+302
2016-06-24	GBE: Fix two bugs in loop preheader.	Ruiling Song	2	-1/+3