Backend: Fix simd id will broke in simd8 mode

Hardware may have bug when mov word from regsiter that not align to 32
bits, add workaroud to force mov from word is always align to 32.

Signed-off-by: Pan Xiuli <xiuli.pan@intel.com>
Reviewed-by: Yang Rong <rong.r.yang@intel.com>

1 files changed, 6 insertions, 4 deletions

diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index 3b21fb53..9a26cdc9 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -1770,13 +1770,15 @@ namespace gbe
   GenRegister Selection::Opaque::getLaneIDReg()
   {
     const GenRegister laneID = GenRegister::immv(0x76543210);
-    ir::Register r = reg(ir::RegisterFamily::FAMILY_WORD);
-    const GenRegister dst = selReg(r, ir::TYPE_U16);
+    GenRegister dst;
 
     uint32_t execWidth = curr.execWidth;
-    if (execWidth == 8)
+    if (execWidth == 8) {
+      // Work around to force the register 32 alignmet
+      dst = selReg(reg(ir::RegisterFamily::FAMILY_DWORD), ir::TYPE_U16);
       MOV(dst, laneID);
-    else {
+    } else {
+      dst = selReg(reg(ir::RegisterFamily::FAMILY_WORD), ir::TYPE_U16);
       push();
       curr.execWidth = 8;
       curr.noMask = 1;