~vlj/llvm - AMDGPU backend development for LLVM

Age	Commit message (Expand)	Author	Files	Lines
2012-10-19	R600: Use native operands for the MOV Instruction	tstellar	3	-2/+3
2012-10-16	Merge master branch	tstellar	83	-406/+7829
2012-10-15	R600: use floor intrinsic instead of llvm.AMDIL.floor	tstellar	1	-2/+2
2012-10-15	R600: use llvm fabs intrinsic	tstellar	1	-2/+2
2012-10-15	R600: add support for cos/sin intrinsic	tstellar	2	-6/+6
2012-10-11	Merge master branch	tstellar	107	-251/+2494
2012-10-09	R600: Handle reversed true/false values in selectcc	tstellar	1	-0/+18
2012-10-09	R600: Prefer lowering SELECT_CC to CND* instructions over SET* instructions	tstellar	1	-0/+16
2012-10-09	R600: Fix lowering of fcmp	tstellar	3	-0/+43
2012-10-09	R600: Add a pattern for: (selectcc i32, -1, i32, i32, SETGT)	tstellar	1	-0/+21
2012-10-09	R600: Add store v4i32 test	tstellar	1	-0/+9
2012-10-09	R600: Add tests for a few vector operations	tstellar	7	-0/+106
2012-10-03	SI: Add sanity test	tstellar	1	-0/+37
2012-10-02	Merge master branch	tstellar	10	-7/+233
2012-10-02	R600: improve select_cc lowering to generate CND* more often	tstellar	2	-0/+22
2012-10-02	Merge master branch	tstellar	74	-99/+3549
2012-10-02	Merge TOT	tstellar	11	-6/+303
2012-09-24	R600: Handle loads from the constants address space.	tstellar	1	-0/+9
2012-09-24	R600: Expand vector fadd and fmul on R600	tstellar	2	-0/+30
2012-09-24	R600: Add support for v4f32 stores on R600	tstellar	1	-0/+9
2012-09-24	R600: Add optimization for FP_ROUND	tstellar	1	-0/+11
2012-09-24	R600: Add support for i8 reads on R600	tstellar	1	-0/+10
2012-09-24	R600: Replace AMDGPU pow intrinsic with the llvm version	tstellar	1	-2/+2
2012-09-24	Address one of the original FIXMEs for the new SROA pass by implementing	tstellar	1	-20/+43
2012-09-24	Emit dtors into proper section while compiling in vcpp-compatible mode.	tstellar	1	-6/+17
2012-09-24	Switch to a signed representation for the dynamic offsets while walking	tstellar	1	-0/+58
2012-09-24	Don't do actual work inside an assert statement. Fixes PR11760!	tstellar	3	-0/+3
2012-09-24	Revise test to avoid using of 'grep'	tstellar	1	-20/+14
2012-09-24	Enhance test case of atomic16 to verify inst encoding fixed in r164453.	tstellar	1	-0/+6
2012-09-24	Fix edge cases of ARM shift operands in arith instructions.	tstellar	2	-0/+88
2012-09-24	Fix the handling of edge cases in ARM shifted operands.	tstellar	2	-0/+116
2012-09-24	Fix a case where the new SROA pass failed to zap dead operands to	tstellar	1	-7/+11
2012-09-24	LoopIdiom: Give up when the loop is not in canonical form.	tstellar	1	-0/+34
2012-09-24	[fast-isel] Fallback to SelectionDAG isel if we require strict alignment for	tstellar	1	-0/+36
2012-09-21	Revert "XXX: Update pow test" This WIP commit was accidently pulled.	tstellar	1	-2/+2
2012-09-21	XXX: Update pow test	Tom Stellard	1	-2/+2
2012-09-21	test/CodeGen/R600: Add checks for register operands	Tom Stellard	13	-15/+15
2012-09-21	test/CodeGen/R600: Add some basic tests	Tom Stellard	14	-0/+227
2012-09-21	InstCombine: Make sure we use the pre-zext type when creating a constant of a...	d0k	1	-0/+14
2012-09-21	BitcodeReader: Correctly insert blockaddress constant referring to a already ...	d0k	1	-0/+15
2012-09-21	Fix SymbolRef::getAddress implementation for ELF. The 'value' field in symbol...	samsonov	2	-9/+25
2012-09-21	llvm/test/CodeGen/X86/pr5145.ll: Tweak expressions to match for darwin target.	chapuni	1	-8/+8
2012-09-21	Add missing i8 max/min/umax/umin support	hliao	2	-1/+35
2012-09-21	llvm/test/CodeGen/ARM/fast-isel.ll: Fix possible typos, s/@unaligned_i16_stor...	chapuni	1	-2/+2
2012-09-21	Testcase does not need to be this strict.	mcrosier	1	-1/+1
2012-09-21	Add newline.	mcrosier	1	-1/+1
2012-09-21	[fast-isel] Fallback to SelectionDAG isel if we require strict alignment for	mcrosier	1	-0/+30
2012-09-21	ARM: Use a dedicated intrinsic for vector bitwise select.	grosbach	1	-0/+49
2012-09-20	Ignore PHI-defs for -new-coalescer interference checks.	stoklund	1	-0/+48
2012-09-20	Only emit DW_AT_object_pointer if this is a definition.	echristo	1	-2/+2