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authorDave Airlie <airlied@linux.ie>2006-12-31 11:44:04 +1100
committerDave Airlie <airlied@linux.ie>2006-12-31 11:44:04 +1100
commitfaa42876486fbf22d49fe1455880e2b8c0aac5ff (patch)
tree6a1e3b658e4e7d58f2159661aa5d0fac51d3f5f2
parent893d60ff43b43d664f394e5ba74e7d812faa9093 (diff)
add some more crtcx registers
-rw-r--r--nouveau_reg.h2
-rw-r--r--radeontool.c9
2 files changed, 9 insertions, 2 deletions
diff --git a/nouveau_reg.h b/nouveau_reg.h
index a880462..d7f3b09 100644
--- a/nouveau_reg.h
+++ b/nouveau_reg.h
@@ -281,3 +281,5 @@
#define NV_RAMDAC_MPLL_B 0x574
#define NV_RAMDAC_VPLL_B 0x578
#define NV_RAMDAC_VPLL2_B 0x57c
+
+#define NV_RAMDAC_FP_CONTROL 0x848
diff --git a/radeontool.c b/radeontool.c
index a2a37db..6af3751 100644
--- a/radeontool.c
+++ b/radeontool.c
@@ -191,10 +191,15 @@ int dump_vga_regs(int crtc)
get_vga_crtc_reg(crtc, i+1), get_vga_crtc_reg(crtc, i+2), get_vga_crtc_reg(crtc, i+3));
#define SHOW_VGA_CRTC_REG(r) printf("%s\t%02x\n", #r, get_vga_crtc_reg(crtc, r))
+ SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_CURCTL0);
+ SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_CURCTL1);
+ SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_CURCTL2);
+ SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_INTERLACE);
SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_REPAINT0);
SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_REPAINT1);
SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_FIFO0);
SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_FIFO1);
+ SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_OWNER);
SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_EXTRA);
SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_LSR);
SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_PIXEL);
@@ -223,6 +228,8 @@ void radeon_cmd_regs(void)
#define SHOW_RAMDAC0_REG(r) printf("%s\t%08x\n", #r, radeon_get32(NV_PRAMDAC0_OFFSET+r, #r))
+ SHOW_RAMDAC0_REG(NV_RAMDAC_FP_CONTROL);
+ SHOW_RAMDAC0_REG(NV_RAMDAC_GENERAL_CONTROL);
SHOW_RAMDAC0_REG(NV_RAMDAC_NVPLL);
SHOW_RAMDAC0_REG(NV_RAMDAC_MPLL);
SHOW_RAMDAC0_REG(NV_RAMDAC_VPLL);
@@ -234,8 +241,6 @@ void radeon_cmd_regs(void)
SHOW_RAMDAC0_REG(NV_RAMDAC_VPLL_B);
SHOW_RAMDAC0_REG(NV_RAMDAC_VPLL2_B);
-
-
dump_vga_regs(0);
dump_vga_regs(1);