diff options
| author | Dave Airlie <airlied@linux.ie> | 2006-12-25 00:45:54 +1100 |
|---|---|---|
| committer | Dave Airlie <airlied@linux.ie> | 2006-12-25 00:45:54 +1100 |
| commit | 893d60ff43b43d664f394e5ba74e7d812faa9093 (patch) | |
| tree | 6c398a34576a6b664f15ef76a7a81d10871928d9 | |
| parent | a55717ba4dd74361737210ddca00ede03830c66e (diff) | |
add nvidia support on branch
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | nouveau_reg.h | 283 | ||||
| -rw-r--r-- | radeontool.c | 1053 |
3 files changed, 419 insertions, 919 deletions
@@ -1,7 +1,7 @@ radeontool: radeontool.c - gcc -Wall -O2 radeontool.c -o radeontool + gcc -g -Wall -O2 radeontool.c -o radeontool diff --git a/nouveau_reg.h b/nouveau_reg.h new file mode 100644 index 0000000..a880462 --- /dev/null +++ b/nouveau_reg.h @@ -0,0 +1,283 @@ + + +#define NV03_BOOT_0 0x00100000 +# define NV03_BOOT_0_RAM_AMOUNT 0x00000003 +# define NV03_BOOT_0_RAM_AMOUNT_8MB 0x00000000 +# define NV03_BOOT_0_RAM_AMOUNT_2MB 0x00000001 +# define NV03_BOOT_0_RAM_AMOUNT_4MB 0x00000002 +# define NV03_BOOT_0_RAM_AMOUNT_8MB_SDRAM 0x00000003 +# define NV04_BOOT_0_RAM_AMOUNT_32MB 0x00000000 +# define NV04_BOOT_0_RAM_AMOUNT_4MB 0x00000001 +# define NV04_BOOT_0_RAM_AMOUNT_8MB 0x00000002 +# define NV04_BOOT_0_RAM_AMOUNT_16MB 0x00000003 + +#define NV04_FIFO_DATA 0x0010020c +# define NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000 +# define NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20 + +#define NV03_PGRAPH_STATUS 0x004006b0 +#define NV04_PGRAPH_STATUS 0x00400700 + +#define NV_RAMIN 0x00700000 + +#define NV_RAMHT_HANDLE_OFFSET 0 +#define NV_RAMHT_CONTEXT_OFFSET 4 +# define NV_RAMHT_CONTEXT_VALID (1<<31) +# define NV_RAMHT_CONTEXT_CHANNEL_SHIFT 24 +# define NV_RAMHT_CONTEXT_ENGINE_SHIFT 16 +# define NV_RAMHT_CONTEXT_ENGINE_SOFTWARE 0 +# define NV_RAMHT_CONTEXT_ENGINE_GRAPHICS 1 +# define NV_RAMHT_CONTEXT_INSTANCE_SHIFT 0 +# define NV40_RAMHT_CONTEXT_CHANNEL_SHIFT 23 +# define NV40_RAMHT_CONTEXT_ENGINE_SHIFT 20 +# define NV40_RAMHT_CONTEXT_INSTANCE_SHIFT 0 + +#define NV_DMA_ACCESS_RW 0 +#define NV_DMA_ACCESS_RO 1 +#define NV_DMA_ACCESS_WO 2 +#define NV_DMA_TARGET_VIDMEM 0 +#define NV_DMA_TARGET_AGP 3 + +#define NV03_FIFO_SIZE 0x8000UL +#define NV_MAX_FIFO_NUMBER 32 +#define NV03_FIFO_REGS_SIZE 0x10000 +#define NV03_FIFO_REGS(i) (0x00800000+i*NV03_FIFO_REGS_SIZE) +# define NV03_FIFO_REGS_DMAPUT(i) (NV03_FIFO_REGS(i)+0x40) +# define NV03_FIFO_REGS_DMAGET(i) (NV03_FIFO_REGS(i)+0x44) + +#define NV_PMC_INTSTAT 0x00000100 +# define NV_PMC_INTSTAT_PFIFO_PENDING (1<< 8) +# define NV_PMC_INTSTAT_PGRAPH_PENDING (1<<12) +# define NV_PMC_INTSTAT_CRTC0_PENDING (1<<24) +# define NV_PMC_INTSTAT_CRTC1_PENDING (1<<25) +# define NV_PMC_INTSTAT_CRTCn_PENDING (3<<24) +#define NV_PMC_INTEN 0x00000140 +# define NV_PMC_INTEN_MASTER_ENABLE (1<< 0) + +#define NV_PGRAPH_INTSTAT 0x00400100 +#define NV04_PGRAPH_INTEN 0x00400140 +#define NV40_PGRAPH_INTEN 0x0040013C +# define NV_PGRAPH_INTR_NOTIFY (1<< 0) +# define NV_PGRAPH_INTR_MISSING_HW (1<< 4) +# define NV_PGRAPH_INTR_CONTEXT_SWITCH (1<<12) +# define NV_PGRAPH_INTR_BUFFER_NOTIFY (1<<16) +# define NV_PGRAPH_INTR_ERROR (1<<20) +#define NV_PGRAPH_CTX_CONTROL 0x00400144 +#define NV_PGRAPH_NV40_UNK220 0x00400220 +# define NV_PGRAPH_NV40_UNK220_FB_INSTANCE +#define NV_PGRAPH_CTX_USER 0x00400148 +#define NV_PGRAPH_CTX_SWITCH1 0x0040014C +#define NV_PGRAPH_FIFO 0x00400720 +#define NV_PGRAPH_FFINTFC_ST2 0x00400764 + +/* It's a guess that this works on NV03. Confirmed on NV04, though */ +#define NV_PFIFO_DELAY_0 0x00002040 +#define NV_PFIFO_DMA_TIMESLICE 0x00002044 +#define NV_PFIFO_INTSTAT 0x00002100 +#define NV_PFIFO_INTEN 0x00002140 +# define NV_PFIFO_INTR_CACHE_ERROR (1<< 0) +# define NV_PFIFO_INTR_RUNOUT (1<< 4) +# define NV_PFIFO_INTR_RUNOUT_OVERFLOW (1<< 8) +# define NV_PFIFO_INTR_DMA_PUSHER (1<<12) +# define NV_PFIFO_INTR_DMA_PT (1<<16) +# define NV_PFIFO_INTR_SEMAPHORE (1<<20) +# define NV_PFIFO_INTR_ACQUIRE_TIMEOUT (1<<24) +#define NV_PFIFO_RAMHT 0x00002210 +#define NV_PFIFO_RAMFC 0x00002214 +#define NV_PFIFO_RAMRO 0x00002218 +#define NV40_PFIFO_RAMFC 0x00002220 +#define NV_PFIFO_CACHES 0x00002500 +#define NV_PFIFO_MODE 0x00002504 +#define NV_PFIFO_DMA 0x00002508 +#define NV_PFIFO_SIZE 0x0000250c +#define NV_PFIFO_CACH0_PSH0 0x00003000 +#define NV_PFIFO_CACH0_PUL0 0x00003050 +#define NV_PFIFO_CACH0_PUL1 0x00003054 +#define NV_PFIFO_CACH1_PSH0 0x00003200 +#define NV_PFIFO_CACH1_PSH1 0x00003204 +#define NV_PFIFO_CACH1_DMAPSH 0x00003220 +#define NV_PFIFO_CACH1_DMAF 0x00003224 +# define NV_PFIFO_CACH1_DMAF_TRIG_8_BYTES 0x00000000 +# define NV_PFIFO_CACH1_DMAF_TRIG_16_BYTES 0x00000008 +# define NV_PFIFO_CACH1_DMAF_TRIG_24_BYTES 0x00000010 +# define NV_PFIFO_CACH1_DMAF_TRIG_32_BYTES 0x00000018 +# define NV_PFIFO_CACH1_DMAF_TRIG_40_BYTES 0x00000020 +# define NV_PFIFO_CACH1_DMAF_TRIG_48_BYTES 0x00000028 +# define NV_PFIFO_CACH1_DMAF_TRIG_56_BYTES 0x00000030 +# define NV_PFIFO_CACH1_DMAF_TRIG_64_BYTES 0x00000038 +# define NV_PFIFO_CACH1_DMAF_TRIG_72_BYTES 0x00000040 +# define NV_PFIFO_CACH1_DMAF_TRIG_80_BYTES 0x00000048 +# define NV_PFIFO_CACH1_DMAF_TRIG_88_BYTES 0x00000050 +# define NV_PFIFO_CACH1_DMAF_TRIG_96_BYTES 0x00000058 +# define NV_PFIFO_CACH1_DMAF_TRIG_104_BYTES 0x00000060 +# define NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES 0x00000068 +# define NV_PFIFO_CACH1_DMAF_TRIG_120_BYTES 0x00000070 +# define NV_PFIFO_CACH1_DMAF_TRIG_128_BYTES 0x00000078 +# define NV_PFIFO_CACH1_DMAF_TRIG_136_BYTES 0x00000080 +# define NV_PFIFO_CACH1_DMAF_TRIG_144_BYTES 0x00000088 +# define NV_PFIFO_CACH1_DMAF_TRIG_152_BYTES 0x00000090 +# define NV_PFIFO_CACH1_DMAF_TRIG_160_BYTES 0x00000098 +# define NV_PFIFO_CACH1_DMAF_TRIG_168_BYTES 0x000000A0 +# define NV_PFIFO_CACH1_DMAF_TRIG_176_BYTES 0x000000A8 +# define NV_PFIFO_CACH1_DMAF_TRIG_184_BYTES 0x000000B0 +# define NV_PFIFO_CACH1_DMAF_TRIG_192_BYTES 0x000000B8 +# define NV_PFIFO_CACH1_DMAF_TRIG_200_BYTES 0x000000C0 +# define NV_PFIFO_CACH1_DMAF_TRIG_208_BYTES 0x000000C8 +# define NV_PFIFO_CACH1_DMAF_TRIG_216_BYTES 0x000000D0 +# define NV_PFIFO_CACH1_DMAF_TRIG_224_BYTES 0x000000D8 +# define NV_PFIFO_CACH1_DMAF_TRIG_232_BYTES 0x000000E0 +# define NV_PFIFO_CACH1_DMAF_TRIG_240_BYTES 0x000000E8 +# define NV_PFIFO_CACH1_DMAF_TRIG_248_BYTES 0x000000F0 +# define NV_PFIFO_CACH1_DMAF_TRIG_256_BYTES 0x000000F8 +# define NV_PFIFO_CACH1_DMAF_SIZE 0x0000E000 +# define NV_PFIFO_CACH1_DMAF_SIZE_32_BYTES 0x00000000 +# define NV_PFIFO_CACH1_DMAF_SIZE_64_BYTES 0x00002000 +# define NV_PFIFO_CACH1_DMAF_SIZE_96_BYTES 0x00004000 +# define NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES 0x00006000 +# define NV_PFIFO_CACH1_DMAF_SIZE_160_BYTES 0x00008000 +# define NV_PFIFO_CACH1_DMAF_SIZE_192_BYTES 0x0000A000 +# define NV_PFIFO_CACH1_DMAF_SIZE_224_BYTES 0x0000C000 +# define NV_PFIFO_CACH1_DMAF_SIZE_256_BYTES 0x0000E000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS 0x001F0000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_0 0x00000000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_1 0x00010000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_2 0x00020000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_3 0x00030000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_4 0x00040000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_5 0x00050000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_6 0x00060000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_7 0x00070000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_8 0x00080000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_9 0x00090000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_10 0x000A0000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_11 0x000B0000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_12 0x000C0000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_13 0x000D0000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_14 0x000E0000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_15 0x000F0000 +# define NV_PFIFO_CACH1_ENDIAN 0x80000000 +# define NV_PFIFO_CACH1_LITTLE_ENDIAN 0x7FFFFFFF +# define NV_PFIFO_CACH1_BIG_ENDIAN 0x80000000 +#define NV_PFIFO_CACH1_DMAS 0x00003228 +#define NV_PFIFO_CACH1_DMAI 0x0000322c +#define NV_PFIFO_CACH1_DMAC 0x00003230 +#define NV_PFIFO_CACH1_DMAP 0x00003240 +#define NV_PFIFO_CACH1_DMAG 0x00003244 +#define NV_PFIFO_CACH1_REF_CNT 0x00003248 +#define NV_PFIFO_CACH1_DMASR 0x0000324C +#define NV_PFIFO_CACH1_PUL0 0x00003250 +#define NV_PFIFO_CACH1_PUL1 0x00003254 +#define NV_PFIFO_CACH1_HASH 0x00003258 +#define NV_PFIFO_CACH1_ACQUIRE_TIMEOUT 0x00003260 +#define NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP 0x00003264 +#define NV_PFIFO_CACH1_ACQUIRE_VALUE 0x00003268 +#define NV_PFIFO_CACH1_SEMAPHORE 0x0000326C +#define NV_PFIFO_CACH1_GET 0x00003270 +#define NV_PFIFO_CACH1_ENG 0x00003280 +#define NV_PFIFO_CACH1_DMA_DCOUNT 0x000032A0 +#define NV40_PFIFO_GRCTX_INSTANCE 0x000032E0 +#define NV40_PFIFO_UNK32E4 0x000032E4 +#define NV_PFIFO_CACH1_METHOD(i) (0x00003800+(i*8)) +#define NV_PFIFO_CACH1_DATA(i) (0x00003804+(i*8)) +#define NV40_PFIFO_CACH1_METHOD(i) (0x00090000+(i*8)) +#define NV40_PFIFO_CACH1_DATA(i) (0x00090004+(i*8)) + +#define NV_CRTC0_INTSTAT 0x00600100 +#define NV_CRTC0_INTEN 0x00600140 +#define NV_CRTC1_INTSTAT 0x00602100 +#define NV_CRTC1_INTEN 0x00602140 +# define NV_CRTC_INTR_VBLANK (1<<0) + +/* Fifo commands. These are not regs, neither masks */ +#define NV03_FIFO_CMD_JUMP 0x20000000 +#define NV03_FIFO_CMD_JUMP_OFFSET_MASK 0x1ffffffc +#define NV03_FIFO_CMD_REWIND (NV03_FIFO_CMD_JUMP | (0 & NV03_FIFO_CMD_JUMP_OFFSET_MASK)) + +/* RAMFC offsets */ +#define NV10_RAMFC_DMA_PUT 0x00 +#define NV10_RAMFC_DMA_GET 0x04 +#define NV10_RAMFC_REF_CNT 0x08 +#define NV10_RAMFC_DMA_INSTANCE 0x0C +#define NV10_RAMFC_DMA_STATE 0x10 +#define NV10_RAMFC_DMA_FETCH 0x14 +#define NV10_RAMFC_ENGINE 0x18 +#define NV10_RAMFC_PULL1_ENGINE 0x1C +#define NV10_RAMFC_ACQUIRE_VALUE 0x20 +#define NV10_RAMFC_ACQUIRE_TIMESTAMP 0x24 +#define NV10_RAMFC_ACQUIRE_TIMEOUT 0x28 +#define NV10_RAMFC_SEMAPHORE 0x2C +#define NV10_RAMFC_DMA_SUBROUTINE 0x30 + +#define NV40_RAMFC_DMA_PUT 0x00 +#define NV40_RAMFC_DMA_GET 0x04 +#define NV40_RAMFC_REF_CNT 0x08 +#define NV40_RAMFC_DMA_INSTANCE 0x0C +#define NV40_RAMFC_DMA_DCOUNT /* ? */ 0x10 +#define NV40_RAMFC_DMA_STATE 0x14 +#define NV40_RAMFC_DMA_FETCH 0x18 +#define NV40_RAMFC_ENGINE 0x1C +#define NV40_RAMFC_PULL1_ENGINE 0x20 +#define NV40_RAMFC_ACQUIRE_VALUE 0x24 +#define NV40_RAMFC_ACQUIRE_TIMESTAMP 0x28 +#define NV40_RAMFC_ACQUIRE_TIMEOUT 0x2C +#define NV40_RAMFC_SEMAPHORE 0x30 +#define NV40_RAMFC_DMA_SUBROUTINE 0x34 +#define NV40_RAMFC_GRCTX_INSTANCE /* guess */ 0x38 +#define NV40_RAMFC_DMA_TIMESLICE 0x3C +#define NV40_RAMFC_UNK_40 0x40 +#define NV40_RAMFC_UNK_44 0x44 +#define NV40_RAMFC_UNK_48 0x48 +#define NV40_RAMFC_2088 0x4C +#define NV40_RAMFC_3300 0x50 + +#define NV_PRAMDAC0_OFFSET 0x00680000 +#define NV_PCRTC0_OFFSET 0x00600000 +#define NV_PCIO0_OFFSET 0x00601000 +#define NV_PCIO0_SIZE 0x00002000 + + + +#define NV_VGA_CRTCX_REPAINT0 0x19 +#define NV_VGA_CRTCX_REPAINT1 0x1a +#define NV_VGA_CRTCX_FIFO0 0x1b +#define NV_VGA_CRTCX_FIFO1 0x1c +#define NV_VGA_CRTCX_LOCK 0x1f +#define NV_VGA_CRTCX_FIFO_LWM 0x20 +#define NV_VGA_CRTCX_BUFFER 0x21 +#define NV_VGA_CRTCX_LSR 0x25 +#define NV_VGA_CRTCX_PIXEL 0x28 +#define NV_VGA_CRTCX_HEB 0x2d +#define NV_VGA_CRTCX_CURCTL2 0x2f +#define NV_VGA_CRTCX_CURCTL0 0x30 +#define NV_VGA_CRTCX_CURCTL1 0x31 +#define NV_VGA_CRTCX_LCD 0x33 +#define NV_VGA_CRTCX_INTERLACE 0x39 +#define NV_VGA_CRTCX_EXTRA 0x41 +#define NV_VGA_CRTCX_OWNER 0x44 +#define NV_VGA_CRTCX_SWAPPING 0x46 +#define NV_VGA_CRTCX_FIFO_LWM_NV30 0x47 +#define NV_VGA_CRTCX_FP_HTIMING 0x53 +#define NV_VGA_CRTCX_FP_VTIMING 0x54 + +#define NV_CRTC_START 0x800 +#define NV_CRTC_HEAD_CONFIG 0x860 + +#define NV_RAMDAC_GENERAL_CONTROL 0x600 + + +#define NV_RAMDAC_NVPLL 0x500 +#define NV_RAMDAC_MPLL 0x504 +# define NV_RAMDAC_PLL_COEFF_MDIV 0x000000FF +# define NV_RAMDAC_PLL_COEFF_NDIV 0x0000FF00 +# define NV_RAMDAC_PLL_COEFF_PDIV 0x00070000 + +#define NV_RAMDAC_VPLL 0x508 +#define NV_RAMDAC_PLL_SELECT 0x50c +#define NV_RAMDAC_VPLL2 0x520 +#define NV_RAMDAC_DITHER_NV11 0x528 +#define NV_RAMDAC_052C 0x52c + +#define NV_RAMDAC_NVPLL_B 0x570 +#define NV_RAMDAC_MPLL_B 0x574 +#define NV_RAMDAC_VPLL_B 0x578 +#define NV_RAMDAC_VPLL2_B 0x57c diff --git a/radeontool.c b/radeontool.c index e7cbf00..a2a37db 100644 --- a/radeontool.c +++ b/radeontool.c @@ -23,10 +23,11 @@ #include <sys/mman.h> #include <asm/page.h> #include <fnmatch.h> +#include <stdint.h> -#include "radeon_reg.h" +#include "nouveau_reg.h" -int debug; +int debug=0; int skip; /* *radeon_cntl_mem is mapped to the actual device's memory mapped control area. */ @@ -39,7 +40,7 @@ static void fatal(char *why) exit (-1); } -static unsigned int radeon_get(unsigned long offset, const char *name) +static unsigned int radeon_get32(unsigned long offset, const char *name) { unsigned int value; if(debug) @@ -61,7 +62,7 @@ static unsigned int radeon_get(unsigned long offset, const char *name) printf("%08x\n",value); return value; } -static void radeon_set(unsigned long offset, const char *name, unsigned int value) +static void radeon_set32(unsigned long offset, const char *name, unsigned int value) { if(debug) printf("writing %s (%lx) -> %08x\n",name,offset,value); @@ -79,16 +80,47 @@ static void radeon_set(unsigned long offset, const char *name, unsigned int valu #endif } +static unsigned int radeon_get8(unsigned long offset, const char *name) +{ + unsigned char value; + if(debug) + printf("reading %s (%lx) is ",name,offset); + if(radeon_cntl_mem == NULL) { + printf("internal error\n"); + exit(-2); + }; +#ifdef __powerpc__ + __asm__ __volatile__ ("lwbrx %0,%1,%2\n\t" + "eieio" + : "=r" (value) + : "b" (radeon_cntl_mem), "r"(offset), + "m" (*((volatile unsigned int *)radeon_cntl_mem+offset))); +#else + value = *(unsigned char * volatile)(radeon_cntl_mem+offset); +#endif + if(debug) + printf("%02x\n",value); + return value; +} + +static void radeon_set8(unsigned long offset, const char *name, unsigned char value) +{ + if(debug) + printf("writing %s (%lx) -> %08x\n",name,offset,value); + if(radeon_cntl_mem == NULL) { + printf("internal error\n"); + exit(-2); + }; + + *(unsigned char * volatile)(radeon_cntl_mem+offset) = value; + +} + static void usage(void) { printf("usage: radeontool [options] [command]\n"); printf(" --debug - show a little debug info\n"); printf(" --skip=1 - use the second radeon card\n"); - printf(" dac [on|off] - power down the external video outputs (%s)\n", - (radeon_get(RADEON_DAC_CNTL,"RADEON_DAC_CNTL")&RADEON_DAC_PDWN)?"off":"on"); - printf(" light [on|off] - power down the backlight (%s)\n", - (radeon_get(RADEON_LVDS_GEN_CNTL,"RADEON_LVDS_GEN_CNTL")&RADEON_LVDS_ON)?"on":"off"); - printf(" stretch [on|off|vert|horiz|auto|manual] - stretching for resolution mismatch \n"); printf(" regs - show a listing of some random registers\n"); printf(" regmatch <pattern> - show registers matching wildcard pattern\n"); printf(" regset <pattern> <value> - set registers matching wildcard pattern\n"); @@ -103,7 +135,7 @@ static void usage(void) static unsigned char * map_devince_memory(unsigned int base,unsigned int length) { int mem_fd; - unsigned char *device_mem; + void *device_mem = NULL; /* open /dev/mem */ if ((mem_fd = open("/dev/mem", O_RDWR) ) < 0) { @@ -111,20 +143,20 @@ static unsigned char * map_devince_memory(unsigned int base,unsigned int length) } /* mmap graphics memory */ - if ((device_mem = malloc(length + (getpagesize()-1))) == NULL) { - fatal("allocation error \n"); - } - if ((unsigned long)device_mem % getpagesize()) - device_mem += getpagesize() - ((unsigned long)device_mem % getpagesize()); - device_mem = (unsigned char *)mmap( + // if ((device_mem = malloc(length + (getpagesize()-1))) == NULL) { + // fatal("allocation error \n"); + // } + // if ((unsigned long)device_mem % getpagesize()) + // device_mem += getpagesize() - ((unsigned long)device_mem % getpagesize()); + device_mem = (void *)mmap( (caddr_t)device_mem, length, PROT_READ|PROT_WRITE, - MAP_SHARED|MAP_FIXED, + MAP_SHARED, mem_fd, base - ); - if ((long)device_mem < 0) { + ); + if (device_mem == MAP_FAILED) { if(debug) fprintf(stderr,"mmap returned %d\n",(int)device_mem); fatal("mmap error \n"); @@ -132,492 +164,89 @@ static unsigned char * map_devince_memory(unsigned int base,unsigned int length) return device_mem; } +#define CRTC_INDEX 0x3d4 +#define CRTC_DATA 0x3d5 + +uint8_t get_vga_crtc_reg(int crtc, int reg) +{ + int offset; + uint8_t retval; + if (crtc==0) + offset = NV_PCIO0_OFFSET; + else + offset = NV_PCIO0_OFFSET + 0x2000; + + radeon_set8(offset+CRTC_INDEX, "CRTC", reg); + retval = radeon_get8(offset+CRTC_DATA, "CRTC") & 0xff; + + return retval; +} + +int dump_vga_regs(int crtc) +{ + int i; + + for (i = 0; i<26; i+=4) + printf("CRTC%2d %02X\t%02X %02X %02X %02X\n", crtc, i, get_vga_crtc_reg(crtc, i), + get_vga_crtc_reg(crtc, i+1), get_vga_crtc_reg(crtc, i+2), get_vga_crtc_reg(crtc, i+3)); + +#define SHOW_VGA_CRTC_REG(r) printf("%s\t%02x\n", #r, get_vga_crtc_reg(crtc, r)) + SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_REPAINT0); + SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_REPAINT1); + SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_FIFO0); + SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_FIFO1); + SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_EXTRA); + SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_LSR); + SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_PIXEL); + SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_HEB); + SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_FIFO_LWM); + SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_FIFO_LWM_NV30); + +} void radeon_cmd_regs(void) { - #define SHOW_REG(r) printf("%s\t%08x\n", #r, radeon_get(r, #r)) - - SHOW_REG(RADEON_DAC_CNTL); - SHOW_REG(RADEON_DAC_CNTL2); - SHOW_REG(RADEON_TV_DAC_CNTL); - SHOW_REG(RADEON_DISP_OUTPUT_CNTL); - SHOW_REG(RADEON_CONFIG_MEMSIZE); - SHOW_REG(RADEON_AUX_SC_CNTL); - SHOW_REG(RADEON_CRTC_EXT_CNTL); - SHOW_REG(RADEON_CRTC_GEN_CNTL); - SHOW_REG(RADEON_CRTC2_GEN_CNTL); - SHOW_REG(RADEON_DEVICE_ID); - SHOW_REG(RADEON_DISP_MISC_CNTL); - SHOW_REG(RADEON_GPIO_MONID); - SHOW_REG(RADEON_GPIO_MONIDB); - SHOW_REG(RADEON_GPIO_CRT2_DDC); - SHOW_REG(RADEON_GPIO_DVI_DDC); - SHOW_REG(RADEON_GPIO_VGA_DDC); - SHOW_REG(RADEON_LVDS_GEN_CNTL); - SHOW_REG(RADEON_FP_GEN_CNTL); - SHOW_REG(RADEON_FP2_GEN_CNTL); - SHOW_REG(RADEON_PIXCLKS_CNTL); + #define SHOW_REG(r) printf("%s\t%08x\n", #r, radeon_get32(r, #r)) + + SHOW_REG(NV_PFIFO_RAMHT); + SHOW_REG(NV_PFIFO_RAMRO); + SHOW_REG(NV_PFIFO_RAMFC); + SHOW_REG(NV40_PFIFO_RAMFC); + + #define SHOW_CRTC0_REG(r) printf("%s\t%08x\n", #r, radeon_get32(NV_PCRTC0_OFFSET+r, #r)) + #define SHOW_CRTC1_REG(r) printf("%s\t%08x\n", #r, radeon_get32(NV_PCRTC0_OFFSET+0x2000+r, #r)) + + SHOW_CRTC0_REG(NV_CRTC_START); + SHOW_CRTC0_REG(NV_CRTC_HEAD_CONFIG); + + SHOW_CRTC1_REG(NV_CRTC_START); + SHOW_CRTC1_REG(NV_CRTC_HEAD_CONFIG); + + #define SHOW_RAMDAC0_REG(r) printf("%s\t%08x\n", #r, radeon_get32(NV_PRAMDAC0_OFFSET+r, #r)) + + SHOW_RAMDAC0_REG(NV_RAMDAC_NVPLL); + SHOW_RAMDAC0_REG(NV_RAMDAC_MPLL); + SHOW_RAMDAC0_REG(NV_RAMDAC_VPLL); + SHOW_RAMDAC0_REG(NV_RAMDAC_PLL_SELECT); + SHOW_RAMDAC0_REG(NV_RAMDAC_VPLL2); + + SHOW_RAMDAC0_REG(NV_RAMDAC_NVPLL_B); + SHOW_RAMDAC0_REG(NV_RAMDAC_MPLL_B); + SHOW_RAMDAC0_REG(NV_RAMDAC_VPLL_B); + SHOW_RAMDAC0_REG(NV_RAMDAC_VPLL2_B); + + + + dump_vga_regs(0); + dump_vga_regs(1); + } -#define REGLIST(r) { #r, RADEON_ ## r } +#define REGLIST(r) { #r, r } static struct { const char *name; unsigned address; } reg_list[] = { - REGLIST(ADAPTER_ID), - REGLIST(AGP_BASE), - REGLIST(AGP_CNTL), - REGLIST(AGP_COMMAND), - REGLIST(AGP_STATUS), - REGLIST(AMCGPIO_A_REG), - REGLIST(AMCGPIO_EN_REG), - REGLIST(AMCGPIO_MASK), - REGLIST(AMCGPIO_Y_REG), - REGLIST(ATTRDR), - REGLIST(ATTRDW), - REGLIST(ATTRX), - REGLIST(AUX_SC_CNTL), - REGLIST(AUX1_SC_BOTTOM), - REGLIST(AUX1_SC_LEFT), - REGLIST(AUX1_SC_RIGHT), - REGLIST(AUX1_SC_TOP), - REGLIST(AUX2_SC_BOTTOM), - REGLIST(AUX2_SC_LEFT), - REGLIST(AUX2_SC_RIGHT), - REGLIST(AUX2_SC_TOP), - REGLIST(AUX3_SC_BOTTOM), - REGLIST(AUX3_SC_LEFT), - REGLIST(AUX3_SC_RIGHT), - REGLIST(AUX3_SC_TOP), - REGLIST(AUX_WINDOW_HORZ_CNTL), - REGLIST(AUX_WINDOW_VERT_CNTL), - REGLIST(BASE_CODE), - REGLIST(BIOS_0_SCRATCH), - REGLIST(BIOS_1_SCRATCH), - REGLIST(BIOS_2_SCRATCH), - REGLIST(BIOS_3_SCRATCH), - REGLIST(BIOS_4_SCRATCH), - REGLIST(BIOS_5_SCRATCH), - REGLIST(BIOS_6_SCRATCH), - REGLIST(BIOS_7_SCRATCH), - REGLIST(BIOS_ROM), - REGLIST(BIST), - REGLIST(BUS_CNTL), - REGLIST(BUS_CNTL1), - REGLIST(CACHE_CNTL), - REGLIST(CACHE_LINE), - REGLIST(CAP0_TRIG_CNTL), - REGLIST(CAP1_TRIG_CNTL), - REGLIST(CAPABILITIES_ID), - REGLIST(CAPABILITIES_PTR), - REGLIST(CLOCK_CNTL_DATA), - REGLIST(CLOCK_CNTL_INDEX), - REGLIST(CLR_CMP_CLR_3D), - REGLIST(CLR_CMP_CLR_DST), - REGLIST(CLR_CMP_CLR_SRC), - REGLIST(CLR_CMP_CNTL), - REGLIST(CLR_CMP_MASK), - REGLIST(CLR_CMP_MASK_3D), - REGLIST(COMMAND), - REGLIST(COMPOSITE_SHADOW_ID), - REGLIST(CONFIG_APER_0_BASE), - REGLIST(CONFIG_APER_1_BASE), - REGLIST(CONFIG_APER_SIZE), - REGLIST(CONFIG_BONDS), - REGLIST(CONFIG_CNTL), - REGLIST(CONFIG_MEMSIZE), - REGLIST(CONFIG_MEMSIZE_EMBEDDED), - REGLIST(CONFIG_REG_1_BASE), - REGLIST(CONFIG_REG_APER_SIZE), - REGLIST(CONFIG_XSTRAP), - REGLIST(CONSTANT_COLOR_C), - REGLIST(CRC_CMDFIFO_ADDR), - REGLIST(CRC_CMDFIFO_DOUT), - REGLIST(CRTC_CRNT_FRAME), - REGLIST(CRTC_DEBUG), - REGLIST(CRTC_EXT_CNTL), - REGLIST(CRTC_EXT_CNTL_DPMS_BYTE), - REGLIST(CRTC_GEN_CNTL), - REGLIST(CRTC2_GEN_CNTL), - REGLIST(CRTC_GUI_TRIG_VLINE), - REGLIST(CRTC_H_SYNC_STRT_WID), - REGLIST(CRTC2_H_SYNC_STRT_WID), - REGLIST(CRTC_H_TOTAL_DISP), - REGLIST(CRTC2_H_TOTAL_DISP), - REGLIST(CRTC_OFFSET), - REGLIST(CRTC2_OFFSET), - REGLIST(CRTC_OFFSET_CNTL), - REGLIST(CRTC2_OFFSET_CNTL), - REGLIST(CRTC_PITCH), - REGLIST(CRTC2_PITCH), - REGLIST(CRTC_STATUS), - REGLIST(CRTC_V_SYNC_STRT_WID), - REGLIST(CRTC2_V_SYNC_STRT_WID), - REGLIST(CRTC_V_TOTAL_DISP), - REGLIST(CRTC2_V_TOTAL_DISP), - REGLIST(CRTC_VLINE_CRNT_VLINE), - REGLIST(CRTC2_CRNT_FRAME), - REGLIST(CRTC2_DEBUG), - REGLIST(CRTC2_GUI_TRIG_VLINE), - REGLIST(CRTC2_STATUS), - REGLIST(CRTC2_VLINE_CRNT_VLINE), - REGLIST(CRTC8_DATA), - REGLIST(CRTC8_IDX), - REGLIST(CUR_CLR0), - REGLIST(CUR_CLR1), - REGLIST(CUR_HORZ_VERT_OFF), - REGLIST(CUR_HORZ_VERT_POSN), - REGLIST(CUR_OFFSET), - REGLIST(CUR2_CLR0), - REGLIST(CUR2_CLR1), - REGLIST(CUR2_HORZ_VERT_OFF), - REGLIST(CUR2_HORZ_VERT_POSN), - REGLIST(CUR2_OFFSET), - REGLIST(DAC_CNTL), - REGLIST(DAC_CNTL2), - REGLIST(TV_DAC_CNTL), - REGLIST(DISP_OUTPUT_CNTL), - REGLIST(DAC_CRC_SIG), - REGLIST(DAC_DATA), - REGLIST(DAC_MASK), - REGLIST(DAC_R_INDEX), - REGLIST(DAC_W_INDEX), - REGLIST(DDA_CONFIG), - REGLIST(DDA_ON_OFF), - REGLIST(DEFAULT_OFFSET), - REGLIST(DEFAULT_PITCH), - REGLIST(DEFAULT_SC_BOTTOM_RIGHT), - REGLIST(DESTINATION_3D_CLR_CMP_VAL), - REGLIST(DESTINATION_3D_CLR_CMP_MSK), - REGLIST(DEVICE_ID), - REGLIST(DISP_MISC_CNTL), - REGLIST(DP_BRUSH_BKGD_CLR), - REGLIST(DP_BRUSH_FRGD_CLR), - REGLIST(DP_CNTL), - REGLIST(DP_CNTL_XDIR_YDIR_YMAJOR), - REGLIST(DP_DATATYPE), - REGLIST(DP_GUI_MASTER_CNTL), - REGLIST(DP_GUI_MASTER_CNTL_C), - REGLIST(DP_MIX), - REGLIST(DP_SRC_BKGD_CLR), - REGLIST(DP_SRC_FRGD_CLR), - REGLIST(DP_WRITE_MASK), - REGLIST(DST_BRES_DEC), - REGLIST(DST_BRES_ERR), - REGLIST(DST_BRES_INC), - REGLIST(DST_BRES_LNTH), - REGLIST(DST_BRES_LNTH_SUB), - REGLIST(DST_HEIGHT), - REGLIST(DST_HEIGHT_WIDTH), - REGLIST(DST_HEIGHT_WIDTH_8), - REGLIST(DST_HEIGHT_WIDTH_BW), - REGLIST(DST_HEIGHT_Y), - REGLIST(DST_LINE_START), - REGLIST(DST_LINE_END), - REGLIST(DST_LINE_PATCOUNT), - REGLIST(DST_OFFSET), - REGLIST(DST_PITCH), - REGLIST(DST_PITCH_OFFSET), - REGLIST(DST_PITCH_OFFSET_C), - REGLIST(DST_WIDTH), - REGLIST(DST_WIDTH_HEIGHT), - REGLIST(DST_WIDTH_X), - REGLIST(DST_WIDTH_X_INCY), - REGLIST(DST_X), - REGLIST(DST_X_SUB), - REGLIST(DST_X_Y), - REGLIST(DST_Y), - REGLIST(DST_Y_SUB), - REGLIST(DST_Y_X), - REGLIST(FLUSH_1), - REGLIST(FLUSH_2), - REGLIST(FLUSH_3), - REGLIST(FLUSH_4), - REGLIST(FLUSH_5), - REGLIST(FLUSH_6), - REGLIST(FLUSH_7), - REGLIST(FOG_3D_TABLE_START), - REGLIST(FOG_3D_TABLE_END), - REGLIST(FOG_3D_TABLE_DENSITY), - REGLIST(FOG_TABLE_INDEX), - REGLIST(FOG_TABLE_DATA), - REGLIST(FP_CRTC_H_TOTAL_DISP), - REGLIST(FP_CRTC_V_TOTAL_DISP), - REGLIST(FP_CRTC2_H_TOTAL_DISP), - REGLIST(FP_CRTC2_V_TOTAL_DISP), - REGLIST(FP_GEN_CNTL), - REGLIST(FP2_GEN_CNTL), - REGLIST(FP_H_SYNC_STRT_WID), - REGLIST(FP_H2_SYNC_STRT_WID), - REGLIST(FP_HORZ_STRETCH), - REGLIST(FP_HORZ2_STRETCH), - REGLIST(FP_V_SYNC_STRT_WID), - REGLIST(FP_VERT_STRETCH), - REGLIST(FP_V2_SYNC_STRT_WID), - REGLIST(FP_VERT2_STRETCH), - REGLIST(FW_CNTL), - REGLIST(FW_STATUS), - REGLIST(GEN_INT_CNTL), - REGLIST(GEN_INT_STATUS), - REGLIST(GENENB), - REGLIST(GENFC_RD), - REGLIST(GENFC_WT), - REGLIST(GENMO_RD), - REGLIST(GENMO_WT), - REGLIST(GENS0), - REGLIST(GENS1), - REGLIST(GPIO_MONID), - REGLIST(GPIO_MONIDB), - REGLIST(GPIO_CRT2_DDC), - REGLIST(GPIO_DVI_DDC), - REGLIST(GPIO_VGA_DDC), - REGLIST(GRPH8_DATA), - REGLIST(GRPH8_IDX), - REGLIST(GUI_DEBUG0), - REGLIST(GUI_DEBUG1), - REGLIST(GUI_DEBUG2), - REGLIST(GUI_DEBUG3), - REGLIST(GUI_DEBUG4), - REGLIST(GUI_DEBUG5), - REGLIST(GUI_DEBUG6), - REGLIST(GUI_SCRATCH_REG0), - REGLIST(GUI_SCRATCH_REG1), - REGLIST(GUI_SCRATCH_REG2), - REGLIST(GUI_SCRATCH_REG3), - REGLIST(GUI_SCRATCH_REG4), - REGLIST(GUI_SCRATCH_REG5), - REGLIST(HEADER), - REGLIST(HOST_DATA0), - REGLIST(HOST_DATA1), - REGLIST(HOST_DATA2), - REGLIST(HOST_DATA3), - REGLIST(HOST_DATA4), - REGLIST(HOST_DATA5), - REGLIST(HOST_DATA6), - REGLIST(HOST_DATA7), - REGLIST(HOST_DATA_LAST), - REGLIST(HOST_PATH_CNTL), - REGLIST(HW_DEBUG), - REGLIST(HW_DEBUG2), - REGLIST(I2C_CNTL_1), - REGLIST(DVI_I2C_CNTL_1), - REGLIST(INTERRUPT_LINE), - REGLIST(INTERRUPT_PIN), - REGLIST(IO_BASE), - REGLIST(LATENCY), - REGLIST(LEAD_BRES_DEC), - REGLIST(LEAD_BRES_LNTH), - REGLIST(LEAD_BRES_LNTH_SUB), - REGLIST(LVDS_GEN_CNTL), - REGLIST(MAX_LATENCY), - REGLIST(MC_AGP_LOCATION), - REGLIST(MC_FB_LOCATION), - REGLIST(MC_STATUS), - REGLIST(MDGPIO_A_REG), - REGLIST(MDGPIO_EN_REG), - REGLIST(MDGPIO_MASK), - REGLIST(MDGPIO_Y_REG), - REGLIST(MEM_ADDR_CONFIG), - REGLIST(MEM_BASE), - REGLIST(MEM_CNTL), - REGLIST(MEM_INIT_LAT_TIMER), - REGLIST(MEM_INTF_CNTL), - REGLIST(MEM_SDRAM_MODE_REG), - REGLIST(MEM_STR_CNTL), - REGLIST(MEM_VGA_RP_SEL), - REGLIST(MEM_VGA_WP_SEL), - REGLIST(MIN_GRANT), - REGLIST(MM_DATA), - REGLIST(MM_INDEX), - REGLIST(MPP_TB_CONFIG), - REGLIST(MPP_GP_CONFIG), - REGLIST(N_VIF_COUNT), - REGLIST(OV0_SCALE_CNTL), - REGLIST(OVR_CLR), - REGLIST(OVR_WID_LEFT_RIGHT), - REGLIST(OVR_WID_TOP_BOTTOM), - REGLIST(OV0_Y_X_START), - REGLIST(OV0_Y_X_END), - REGLIST(OV0_EXCLUSIVE_HORZ), - REGLIST(OV0_EXCLUSIVE_VERT), - REGLIST(OV0_REG_LOAD_CNTL), - REGLIST(OV0_SCALE_CNTL), - REGLIST(OV0_V_INC), - REGLIST(OV0_P1_V_ACCUM_INIT), - REGLIST(OV0_P23_V_ACCUM_INIT), - REGLIST(OV0_P1_BLANK_LINES_AT_TOP), - REGLIST(OV0_P23_BLANK_LINES_AT_TOP), - REGLIST(OV0_VID_BUF0_BASE_ADRS), - REGLIST(OV0_VID_BUF1_BASE_ADRS), - REGLIST(OV0_VID_BUF2_BASE_ADRS), - REGLIST(OV0_VID_BUF3_BASE_ADRS), - REGLIST(OV0_VID_BUF4_BASE_ADRS), - REGLIST(OV0_VID_BUF5_BASE_ADRS), - REGLIST(OV0_VID_BUF_PITCH0_VALUE), - REGLIST(OV0_VID_BUF_PITCH1_VALUE), - REGLIST(OV0_AUTO_FLIP_CNTL), - REGLIST(OV0_DEINTERLACE_PATTERN), - REGLIST(OV0_H_INC), - REGLIST(OV0_STEP_BY), - REGLIST(OV0_P1_H_ACCUM_INIT), - REGLIST(OV0_P23_H_ACCUM_INIT), - REGLIST(OV0_P1_X_START_END), - REGLIST(OV0_P2_X_START_END), - REGLIST(OV0_P3_X_START_END), - REGLIST(OV0_FILTER_CNTL), - REGLIST(OV0_FOUR_TAP_COEF_0), - REGLIST(OV0_FOUR_TAP_COEF_1), - REGLIST(OV0_FOUR_TAP_COEF_2), - REGLIST(OV0_FOUR_TAP_COEF_3), - REGLIST(OV0_FOUR_TAP_COEF_4), - REGLIST(OV0_COLOUR_CNTL), - REGLIST(OV0_VIDEO_KEY_CLR), - REGLIST(OV0_VIDEO_KEY_MSK), - REGLIST(OV0_GRAPHICS_KEY_CLR), - REGLIST(OV0_GRAPHICS_KEY_MSK), - REGLIST(OV0_KEY_CNTL), - REGLIST(OV0_TEST), - REGLIST(PALETTE_DATA), - REGLIST(PALETTE_30_DATA), - REGLIST(PALETTE_INDEX), - REGLIST(PCI_GART_PAGE), - REGLIST(PIXCLKS_CNTL), - REGLIST(PLANE_3D_MASK_C), - REGLIST(PMI_CAP_ID), - REGLIST(PMI_DATA), - REGLIST(PMI_NXT_CAP_PTR), - REGLIST(PMI_PMC_REG), - REGLIST(PMI_PMCSR_REG), - REGLIST(PMI_REGISTER), - REGLIST(PWR_MNGMT_CNTL_STATUS), - REGLIST(DSTCACHE_MODE), - REGLIST(RBBM_SOFT_RESET), - REGLIST(RBBM_STATUS), - REGLIST(RB2D_DSTCACHE_CTLSTAT), - REGLIST(RB2D_DSTCACHE_MODE), - REGLIST(REG_BASE), - REGLIST(REGPROG_INF), - REGLIST(REVISION_ID), - REGLIST(SC_BOTTOM), - REGLIST(SC_BOTTOM_RIGHT), - REGLIST(SC_BOTTOM_RIGHT_C), - REGLIST(SC_LEFT), - REGLIST(SC_RIGHT), - REGLIST(SC_TOP), - REGLIST(SC_TOP_LEFT), - REGLIST(SC_TOP_LEFT_C), - REGLIST(SDRAM_MODE_REG), - REGLIST(SEQ8_DATA), - REGLIST(SEQ8_IDX), - REGLIST(SNAPSHOT_F_COUNT), - REGLIST(SNAPSHOT_VH_COUNTS), - REGLIST(SNAPSHOT_VIF_COUNT), - REGLIST(SRC_OFFSET), - REGLIST(SRC_PITCH), - REGLIST(SRC_PITCH_OFFSET), - REGLIST(SRC_SC_BOTTOM), - REGLIST(SRC_SC_BOTTOM_RIGHT), - REGLIST(SRC_SC_RIGHT), - REGLIST(SRC_X), - REGLIST(SRC_X_Y), - REGLIST(SRC_Y), - REGLIST(SRC_Y_X), - REGLIST(STATUS), - REGLIST(SUBPIC_CNTL), - REGLIST(SUB_CLASS), - REGLIST(SURFACE_CNTL), - REGLIST(SURFACE0_INFO), - REGLIST(SURFACE0_LOWER_BOUND), - REGLIST(SURFACE0_UPPER_BOUND), - REGLIST(SURFACE1_INFO), - REGLIST(SURFACE1_LOWER_BOUND), - REGLIST(SURFACE1_UPPER_BOUND), - REGLIST(SURFACE2_INFO), - REGLIST(SURFACE2_LOWER_BOUND), - REGLIST(SURFACE2_UPPER_BOUND), - REGLIST(SURFACE3_INFO), - REGLIST(SURFACE3_LOWER_BOUND), - REGLIST(SURFACE3_UPPER_BOUND), - REGLIST(SURFACE4_INFO), - REGLIST(SURFACE4_LOWER_BOUND), - REGLIST(SURFACE4_UPPER_BOUND), - REGLIST(SURFACE5_INFO), - REGLIST(SURFACE5_LOWER_BOUND), - REGLIST(SURFACE5_UPPER_BOUND), - REGLIST(SURFACE6_INFO), - REGLIST(SURFACE6_LOWER_BOUND), - REGLIST(SURFACE6_UPPER_BOUND), - REGLIST(SURFACE7_INFO), - REGLIST(SURFACE7_LOWER_BOUND), - REGLIST(SURFACE7_UPPER_BOUND), - REGLIST(SW_SEMAPHORE), - REGLIST(TEST_DEBUG_CNTL), - REGLIST(TEST_DEBUG_MUX), - REGLIST(TEST_DEBUG_OUT), - REGLIST(TMDS_CRC), - REGLIST(TRAIL_BRES_DEC), - REGLIST(TRAIL_BRES_ERR), - REGLIST(TRAIL_BRES_INC), - REGLIST(TRAIL_X), - REGLIST(TRAIL_X_SUB), - REGLIST(PIXCLKS_CNTL), - REGLIST(VENDOR_ID), - REGLIST(VGA_DDA_CONFIG), - REGLIST(VGA_DDA_ON_OFF), - REGLIST(VID_BUFFER_CONTROL), - REGLIST(VIDEOMUX_CNTL), - REGLIST(VIPH_CONTROL), - REGLIST(WAIT_UNTIL), - REGLIST(RB3D_BLENDCNTL), - REGLIST(RB3D_CNTL), - REGLIST(RB3D_COLOROFFSET), - REGLIST(RB3D_COLORPITCH), - REGLIST(RB3D_DEPTHOFFSET), - REGLIST(RB3D_DEPTHPITCH), - REGLIST(RB3D_PLANEMASK), - REGLIST(RB3D_ROPCNTL), - REGLIST(RB3D_STENCILREFMASK), - REGLIST(RB3D_ZSTENCILCNTL), - REGLIST(RB3D_DSTCACHE_MODE), - REGLIST(RE_LINE_PATTERN), - REGLIST(RE_LINE_STATE), - REGLIST(RE_MISC), - REGLIST(RE_SOLID_COLOR), - REGLIST(RE_TOP_LEFT), - REGLIST(RE_WIDTH_HEIGHT), - REGLIST(LVDS_PLL_CNTL), - REGLIST(TMDS_PLL_CNTL), - REGLIST(TMDS_TRANSMITTER_CNTL), - REGLIST(ISYNC_CNTL), - REGLIST(TV_MASTER_CNTL), - REGLIST(TV_PRE_DAC_MUX_CNTL), - REGLIST(TV_RGB_CNTL), - REGLIST(TV_SYNC_CNTL), - REGLIST(TV_HTOTAL), - REGLIST(TV_HDISP), - REGLIST(TV_HSTART), - REGLIST(TV_HCOUNT), - REGLIST(TV_VTOTAL), - REGLIST(TV_VDISP), - REGLIST(TV_VCOUNT), - REGLIST(TV_FTOTAL), - REGLIST(TV_FCOUNT), - REGLIST(TV_FRESTART), - REGLIST(TV_HRESTART), - REGLIST(TV_VRESTART), - REGLIST(TV_VSCALER_CNTL1), - REGLIST(TV_TIMING_CNTL), - REGLIST(TV_VSCALER_CNTL2), - REGLIST(TV_Y_FALL_CNTL), - REGLIST(TV_Y_RISE_CNTL), - REGLIST(TV_Y_SAW_TOOTH_CNTL), - REGLIST(TV_UPSAMP_AND_GAIN_CNTL), - REGLIST(TV_GAIN_LIMIT_SETTINGS), - REGLIST(TV_LINEAR_GAIN_SETTINGS), - REGLIST(TV_MODULATOR_CNTL1), - REGLIST(TV_MODULATOR_CNTL2), - REGLIST(TV_CRC_CNTL), - REGLIST(TV_UV_ADR), - REGLIST(GPIOPAD_A), + REGLIST(NV40_PFIFO_RAMFC), }; void radeon_reg_match(const char *pattern) @@ -627,7 +256,7 @@ void radeon_reg_match(const char *pattern) if (fnmatch(pattern, reg_list[i].name, 0) == 0) { printf("%s (%04x)\t0x%08x\n", reg_list[i].name, reg_list[i].address, - radeon_get(reg_list[i].address, reg_list[i].name)); + radeon_get32(reg_list[i].address, reg_list[i].name)); } } } @@ -639,110 +268,13 @@ void radeon_reg_set(const char *name, unsigned value) if (fnmatch(name, reg_list[i].name, 0) == 0) { const char *name = reg_list[i].name; unsigned address = reg_list[i].address; - printf("OLD: %s (%04x)\t0x%08x\n", name, address, radeon_get(address, name)); - radeon_set(address, name, value); - printf("NEW: %s (%04x)\t0x%08x\n", name, address, radeon_get(address, name)); + printf("OLD: %s (%04x)\t0x%08x\n", name, address, radeon_get32(address, name)); + radeon_set32(address, name, value); + printf("NEW: %s (%04x)\t0x%08x\n", name, address, radeon_get32(address, name)); } } } -void radeon_cmd_bits(void) -{ - unsigned int dac_cntl; - - dac_cntl = radeon_get(RADEON_DAC_CNTL,"RADEON_DAC_CNTL"); - printf("RADEON_DAC_CNTL=%08x (",dac_cntl); - if(dac_cntl & RADEON_DAC_RANGE_CNTL) - printf("range_cntl "); - if(dac_cntl & RADEON_DAC_BLANKING) - printf("blanking "); - if(dac_cntl & RADEON_DAC_8BIT_EN) - printf("8bit_en "); - if(dac_cntl & RADEON_DAC_VGA_ADR_EN) - printf("vga_adr_en "); - if(dac_cntl & RADEON_DAC_PDWN) - printf("pdwn "); - printf(")\n"); -} - -void radeon_cmd_dac(char *param) -{ - unsigned long dac_cntl; - - dac_cntl = radeon_get(RADEON_DAC_CNTL,"RADEON_DAC_CNTL"); - if(param == NULL) { - printf("The radeon external DAC looks %s\n",(dac_cntl&(RADEON_DAC_PDWN))?"off":"on"); - exit (-1); - } else if(strcmp(param,"off") == 0) { - dac_cntl |= RADEON_DAC_PDWN; - } else if(strcmp(param,"on") == 0) { - dac_cntl &= ~ RADEON_DAC_PDWN; - } else { - usage(); - }; - radeon_set(RADEON_DAC_CNTL,"RADEON_DAC_CNTL",dac_cntl); -} - -void radeon_cmd_light(char *param) -{ - unsigned long lvds_gen_cntl; - - lvds_gen_cntl = radeon_get(RADEON_LVDS_GEN_CNTL,"RADEON_LVDS_GEN_CNTL"); - if(param == NULL) { - printf("The radeon backlight looks %s\n",(lvds_gen_cntl&(RADEON_LVDS_ON))?"on":"off"); - exit (-1); - } else if(strcmp(param,"on") == 0) { - lvds_gen_cntl |= RADEON_LVDS_ON; - } else if(strcmp(param,"off") == 0) { - lvds_gen_cntl &= ~ RADEON_LVDS_ON; - } else { - usage(); - }; - radeon_set(RADEON_LVDS_GEN_CNTL,"RADEON_LVDS_GEN_CNTL",lvds_gen_cntl); -} - -void radeon_cmd_stretch(char *param) -{ - unsigned long fp_vert_stretch,fp_horz_stretch; - - fp_vert_stretch = radeon_get(RADEON_FP_VERT_STRETCH,"RADEON_FP_VERT_STRETCH"); - fp_horz_stretch = radeon_get(RADEON_FP_HORZ_STRETCH,"RADEON_FP_HORZ_STRETCH"); - if(param == NULL) { - printf("The horizontal stretching looks %s\n",(fp_horz_stretch&(RADEON_HORZ_STRETCH_ENABLE))?"on":"off"); - printf("The vertical stretching looks %s\n",(fp_vert_stretch&(RADEON_VERT_STRETCH_ENABLE))?"on":"off"); - exit (-1); - } else if(strncmp(param,"ver",3) == 0) { - fp_horz_stretch &= ~ RADEON_HORZ_STRETCH_ENABLE; - fp_vert_stretch |= RADEON_VERT_STRETCH_ENABLE; - } else if(strncmp(param,"hor",3) == 0) { - fp_horz_stretch |= RADEON_HORZ_STRETCH_ENABLE; - fp_vert_stretch &= ~ RADEON_VERT_STRETCH_ENABLE; - } else if(strcmp(param,"on") == 0) { - fp_horz_stretch |= RADEON_HORZ_STRETCH_ENABLE; - fp_vert_stretch |= RADEON_VERT_STRETCH_ENABLE; - } else if(strcmp(param,"auto") == 0) { - fp_horz_stretch |= RADEON_HORZ_AUTO_RATIO; - fp_horz_stretch |= RADEON_HORZ_AUTO_RATIO_INC; - fp_horz_stretch |= RADEON_HORZ_STRETCH_ENABLE; - fp_vert_stretch |= RADEON_VERT_AUTO_RATIO_EN; - fp_vert_stretch |= RADEON_VERT_STRETCH_ENABLE; - } else if(strcmp(param,"manual") == 0) { - fp_horz_stretch &= ~ RADEON_HORZ_AUTO_RATIO; - fp_horz_stretch &= ~ RADEON_HORZ_AUTO_RATIO_INC; - fp_horz_stretch |= RADEON_HORZ_STRETCH_ENABLE; - fp_vert_stretch &= ~ RADEON_VERT_AUTO_RATIO_EN; - fp_vert_stretch |= RADEON_VERT_STRETCH_ENABLE; - } else if(strcmp(param,"off") == 0) { - fp_horz_stretch &= ~ RADEON_HORZ_STRETCH_ENABLE; - fp_vert_stretch &= ~ RADEON_VERT_STRETCH_ENABLE; - } else { - usage(); - }; - radeon_set(RADEON_FP_HORZ_STRETCH,"RADEON_FP_HORZ_STRETCH",fp_horz_stretch); - radeon_set(RADEON_FP_VERT_STRETCH,"RADEON_FP_VERT_STRETCH",fp_vert_stretch); -} - - /* Here we fork() and exec() the lspci command to look for the Radeon hardware address. */ static void map_radeon_cntl_mem(void) { @@ -803,7 +335,7 @@ We need to look through it to find the smaller region base address f8fffc00. if(fgets(line,sizeof(line),fp) == NULL) { /* if end of file */ fatal("Radeon hardware not found in lspci output.\n"); } - if(strstr(line,"Radeon") || strstr(line,"ATI Tech")) { /* if line contains a "radeon" string */ + if(strstr(line,"nVidia") || strstr(line,"nVidia Corp")) { /* if line contains a "radeon" string */ if(skip-- < 1) { break; } @@ -817,7 +349,7 @@ We need to look through it to find the smaller region base address f8fffc00. } if(debug) printf("%s",line); - if(strstr(line,"emory") && strstr(line,"K")) { /* if line contains a "Memory" and "K" string */ + if(strstr(line,"emory") && strstr(line,"M")) { /* if line contains a "Memory" and "K" string */ break; } }; @@ -826,7 +358,7 @@ We need to look through it to find the smaller region base address f8fffc00. } if(debug) printf("Radeon found. Base control address is %x.\n",base); - radeon_cntl_mem = map_devince_memory(base,0x4000); + radeon_cntl_mem = map_devince_memory(base,0x700000); } #ifdef __powerpc__ @@ -872,297 +404,6 @@ const char *radeon_valname(const struct nametable_entry *table, unsigned int val return ret_buf; } -static struct nametable_entry hdr_type_name[] = { - { 2, "Rage128 & Pro"}, - { 3, "Rage M3"}, - { 4, "Radeon"}, - { 36, "ATOM" }, - { 0, NULL} -}; - -static void radeon_rom_legacy_clocks(unsigned char *bios, int hdr) -{ - int pll_info_block = BIOS16(hdr + 0x30); - - if (pll_info_block == 0) { - printf("No clock info block in BIOS\n"); - return; - } - printf("Clock info block:\n"); - printf(" SCLK : %f\n", BIOS16(pll_info_block + 0x08) / 100.0); - printf(" MCLK : %f\n", BIOS16(pll_info_block + 0x0a) / 100.0); - printf(" RefClk : %f\n", BIOS16(pll_info_block + 0x0e) / 100.0); - printf(" RefDiv : %d\n", BIOS16(pll_info_block + 0x10)); - printf(" VCO Min: %f\n", BIOS32(pll_info_block + 0x12) / 100.0); - printf(" VCO Max: %f\n", BIOS32(pll_info_block + 0x16) / 100.0); - printf("\n"); -} - -static void radeon_rom_atom_clocks(unsigned char *bios, int master) -{ - - int pll_info_block = BIOS16(master + 12); - - if (pll_info_block == 0) { - printf("No clock info block in BIOS\n"); - } - - printf("Clock info block:\n"); - printf(" SCLK : %f\n", BIOS32(pll_info_block + 8) / 100.0); - printf(" MCLK : %f\n", BIOS32(pll_info_block + 12) / 100.0); - printf(" RefClk : %f\n", BIOS16(pll_info_block + 82) / 100.0); - printf(" PPLL Min: %f\n", BIOS16(pll_info_block + 78) / 100.0); - printf(" PPLL Max: %f\n", BIOS32(pll_info_block + 32) / 100.0); -} - - -static struct nametable_entry lconn_type_name[] = { - { 0, "None"}, - { 1, "Proprietary"}, - { 2, "VGA"}, - { 3, "DVI-I"}, - { 4, "DVI-D"}, - { 5, "CTV"}, - { 6, "STV"}, - { 7, "Unsupported"}, - { 0, NULL} -}; - -static struct nametable_entry lddc_type_name[] = { - { 0, "None"}, - { 1, "MONID"}, - { 2, "DVI"}, - { 3, "VGA"}, - { 4, "CRT2"}, - { 0, NULL} -}; - -static struct nametable_entry ldac_type_name[] = { - { 0, "CRT"}, - { 1, "TV"}, - { 2, "External"}, - { 0, NULL} -}; - -static void radeon_rom_legacy_connectors(unsigned char *bios, int hdr) -{ - int offset = BIOS16(hdr + 0x50); - int i, entry, tmp, chips, entries; - - if (offset == 0) { - printf("No connector table in BIOS\n"); - return; - } - - printf("Connector table:\n"); - -#if 0 - printf(" raw: %02x %02x %02x %02x %02x %02x %02x %02x\n", - BIOS8(offset+0), BIOS8(offset+1), BIOS8(offset+2), - BIOS8(offset+3), BIOS8(offset+4), BIOS8(offset+5), - BIOS8(offset+6), BIOS8(offset+7)); -#endif - - - chips = BIOS8(offset) >> 4; - printf(" Table revision %d for %d chip(s)\n", - BIOS8(offset) & 0xf, chips); - if (chips > 1) - printf(" Only 1 chip supported for now !\n"); - entries = BIOS8(offset + 1) & 0xf; - printf(" Table for chip %d has %d connector(s):\n", - BIOS8(offset + 1) >> 4, entries); - for (i = 0; i < 4; i++) { - entry = offset + 2 + i*2; - - /* End of table */ - if (!BIOS16(entry)) { - if (i < entries) - printf(" <table early termination !>\n"); - break; - } - - /* Read table entry, check connector type */ - tmp = BIOS16(entry); - printf(" %08x ", tmp); - printf("Type:%s", radeon_valname(lconn_type_name, - (tmp >> 12) & 0xf)); - printf(", DDC:%s", radeon_valname(lddc_type_name, - (tmp >> 8) & 0xf)); - printf(", DAC:%s", radeon_valname(ldac_type_name, tmp & 0x3)); - printf(", TMDS:%s", (tmp & 0x10) ? "External" : "Internal"); - - printf("\n"); - } - printf("\n"); -} - -static struct nametable_entry atomconn_type_name[] = { - { 0, "None"}, - { 1, "VGA"}, - { 2, "DVI-I"}, - { 3, "DVI-D"}, - { 4, "DVI-A"}, - { 5, "STV"}, - { 6, "CTV"}, - { 7, "LVDS"}, - { 8, "Digital"}, - { 9, "Unsupported"}, - { 0, NULL} -}; - -static void radeon_rom_atom_connectors(unsigned char *bios, int master) -{ - int offset = BIOS16(master + 22); - int tmp, i, tmp0; - int crtc, dac, connector, ddc=0; - - if (offset == 0) { - printf("No connector table in BIOS\n"); - return; - } - - tmp = BIOS16(offset + 4); - printf("Connector table:\n"); - for (i=0; i<8; i++) { - if (tmp & (1<<i)) { - int portinfo = BIOS16(offset+6+i*2); - - crtc = (portinfo >> 8) & 0xf; - dac = (portinfo & 0xf) - 1; - connector = (portinfo >> 4) & 0xf; - - tmp0 = BIOS16(master + 24); - if (1/*crtc*/) { - int gpio = BIOS16(tmp0 + 4 + 27 * crtc) * 4; - printf("gpio is %02X\n", gpio); - switch(gpio) - { - case RADEON_GPIO_MONID: ddc = 1; break; - case RADEON_GPIO_DVI_DDC: ddc = 2; break; - case RADEON_GPIO_VGA_DDC: ddc = 3; break; - case RADEON_GPIO_CRT2_DDC: ddc = 4; break; - default: ddc=0; break; - } - } - - printf("%d: %08x ", i, portinfo); - printf(", Id:%d", crtc); - printf(", Type:%s", radeon_valname(atomconn_type_name, connector)); - if (1/*crtc*/) - printf(", DDC:%s", radeon_valname(lddc_type_name, - ddc)); - printf(", DAC:%s", radeon_valname(ldac_type_name, dac)); - if (i==3) - printf(" TMDS: Internal\n"); - else if (i==7) - printf(" TMDS: External\n"); - else - printf("\n"); - - } - } -} - -static void radeon_rom_legacy_dfptable(unsigned char *bios, int hdr) -{ - int offset, i, n, rev, stride; - - offset = BIOS16(hdr + 0x34); - if (offset == 0) { - printf("No DFP info table\n"); - return; - } - rev = BIOS8(offset); - printf("DFP table revision: %d\n", rev); - - switch(rev) { - case 3: - n = BIOS8(offset + 5) + 1; - if (n > 4) - n = 4; - for (i = 0; i < n; i++) { - /* Looks weird ... but that's what is in X.org */ - printf(" PixClock: %f\t TMDS_PLL_CNTL: %08x\n", - BIOS16(offset+i*10+0x10) / 100.0, - BIOS32(offset+i*10+0x08)); - } - break; - - /* revision 4 has some problem as it appears in RV280... - */ - case 4: - stride = 0; - n = BIOS8(offset+ 5) + 1; - if (n > 4) - n = 4; - for (i = 0; i < n; i++) { - printf(" PixClock: %f\t TMDS_PLL_CNTL: %08x\n", - BIOS16(offset+stride+0x10) / 100.0, - BIOS32(offset+stride+0x08)); - if (i == 0) - stride += 10; - else - stride += 6; - } - break; - } -} - -static void radeon_rom_legacy_exttmdstable(unsigned char *bios, int hdr) -{ - if (BIOS16(hdr + 0x58)) { - printf("Found External TMDS Table\n"); - } - -} - -void radeon_rom_tables(const char * file) -{ -#define _64K (64*1024) - unsigned char bios[_64K]; - int fd, hdr, atom; - - fd = open(file, O_RDONLY); - if (fd < 0) { - perror("can't open rom file"); - return; - } - memset(bios, 0, _64K); - read(fd, bios, _64K); - close(fd); - - if (bios[0] != 0x55 || bios[1] != 0xaa) - fatal("PCI ROM signature 0x55 0xaa missing"); - hdr = BIOS16(0x48); - printf("\nBIOS Tables:\n------------\n\n"); - printf("Header at %x, type: %d [%s]\n", hdr, BIOS8(hdr), - radeon_valname(hdr_type_name, BIOS8(hdr))); - printf("OEM ID: %02x %02x\n", BIOS8(hdr+2), BIOS8(hdr+3)); - atom = (BIOS8(hdr+4) == 'A' && - BIOS8(hdr+5) == 'T' && - BIOS8(hdr+6) == 'O' && - BIOS8(hdr+7) == 'M') || - (BIOS8(hdr+4) == 'M' && - BIOS8(hdr+5) == 'O' && - BIOS8(hdr+6) == 'T' && - BIOS8(hdr+7) == 'A'); - if (atom) { - int master = BIOS16(hdr+32); - printf("ATOM BIOS detected !\n\n"); - radeon_rom_atom_clocks(bios, master); - radeon_rom_atom_connectors(bios, master); - // add more ... - } else { - printf("Legacy BIOS detected !\n"); - printf("BIOS Rev: %x.%x\n\n", BIOS8(hdr+4), BIOS8(hdr+5)); - radeon_rom_legacy_clocks(bios, hdr); - radeon_rom_legacy_connectors(bios, hdr); - radeon_rom_legacy_dfptable(bios, hdr); - radeon_rom_legacy_exttmdstable(bios, hdr); - } -} - int main(int argc,char *argv[]) { if(argc == 1) { @@ -1173,7 +414,7 @@ int main(int argc,char *argv[]) debug=1; argv++; argc--; }; - if(strcmp(argv[1],"--skip=") == 0) { + if(argc && (strcmp(argv[1],"--skip=") == 0)) { skip=atoi(argv[1]+7); argv++; argc--; }; @@ -1182,35 +423,11 @@ int main(int argc,char *argv[]) if(strcmp(argv[1],"regs") == 0) { radeon_cmd_regs(); return 0; - } else if(strcmp(argv[1],"bits") == 0) { - radeon_cmd_bits(); - return 0; - } else if(strcmp(argv[1],"dac") == 0) { - radeon_cmd_dac(NULL); - return 0; - } else if(strcmp(argv[1],"light") == 0) { - radeon_cmd_light(NULL); - return 0; - } else if(strcmp(argv[1],"stretch") == 0) { - radeon_cmd_stretch(NULL); - return 0; }; } else if(argc == 3) { - if(strcmp(argv[1],"dac") == 0) { - radeon_cmd_dac(argv[2]); - return 0; - } else if(strcmp(argv[1],"light") == 0) { - radeon_cmd_light(argv[2]); - return 0; - } else if(strcmp(argv[1],"stretch") == 0) { - radeon_cmd_stretch(argv[2]); - return 0; - } else if(strcmp(argv[1],"regmatch") == 0) { + if(strcmp(argv[1],"regmatch") == 0) { radeon_reg_match(argv[2]); return 0; - } else if(strcmp(argv[1],"romtables") == 0) { - radeon_rom_tables(argv[2]); - return 0; }; } else if(argc == 4) { if(strcmp(argv[1],"regset") == 0) { |