add more nvidia dualhead regs

2 files changed, 32 insertions, 24 deletions

diff --git a/nouveau_reg.h b/nouveau_reg.h
index 8fba2fa..7f1793b 100644
--- a/nouveau_reg.h
+++ b/nouveau_reg.h
@@ -231,6 +231,7 @@
 #define NV40_RAMFC_3300                                          0x50
 
 #define NV_PRAMDAC0_OFFSET          0x00680000
+#define NV_PRAMDAC1_OFFSET          0x00682000
 #define NV_PCRTC0_OFFSET            0x00600000
 #define NV_PCIO0_OFFSET             0x00601000
 #define NV_PCIO0_SIZE               0x00002000
diff --git a/radeontool.c b/radeontool.c
index d2eeac8..35057cd 100644
--- a/radeontool.c
+++ b/radeontool.c
@@ -205,10 +205,11 @@ int dump_vga_regs(int crtc)
   SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_PIXEL);
   SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_HEB);
   SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_FIFO_LWM);
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_BUFFER);
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_OWNER);
   SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_FIFO_LWM_NV30);
+  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_BUFFER);
   
+  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_FP_HTIMING);
+  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_FP_VTIMING);
 }
 void radeon_cmd_regs(void)
 {
@@ -219,8 +220,8 @@ void radeon_cmd_regs(void)
   SHOW_REG(NV_PFIFO_RAMFC);
   SHOW_REG(NV40_PFIFO_RAMFC);
   
-	#define SHOW_CRTC0_REG(r) printf("%s\t%08x\n", #r, radeon_get32(NV_PCRTC0_OFFSET+r, #r))
-	#define SHOW_CRTC1_REG(r) printf("%s\t%08x\n", #r, radeon_get32(NV_PCRTC0_OFFSET+0x2000+r, #r))
+#define SHOW_CRTC0_REG(r) printf("%s\t%08x\n", #r, radeon_get32(NV_PCRTC0_OFFSET+r, #r))
+#define SHOW_CRTC1_REG(r) printf("%s\t%08x\n", #r, radeon_get32(NV_PCRTC0_OFFSET+0x2000+r, #r))
 
   SHOW_CRTC0_REG(NV_CRTC_START);
   SHOW_CRTC0_REG(NV_CRTC_CURSOR_CONFIG);
@@ -232,26 +233,32 @@ void radeon_cmd_regs(void)
   SHOW_CRTC1_REG(NV_CRTC_START);
   SHOW_CRTC1_REG(NV_CRTC_CURSOR_CONFIG);
   SHOW_CRTC1_REG(NV_CRTC_HEAD_CONFIG);
-
-	#define SHOW_RAMDAC0_REG(r) printf("%s\t%08x\n", #r, radeon_get32(NV_PRAMDAC0_OFFSET+r, #r))
-
-  SHOW_RAMDAC0_REG(NV_RAMDAC_CURSOR_POS);
-  SHOW_RAMDAC0_REG(NV_RAMDAC_CURSOR_CTRL);
-  SHOW_RAMDAC0_REG(NV_RAMDAC_CURSOR_DATA_LO);
-  SHOW_RAMDAC0_REG(NV_RAMDAC_CURSOR_DATA_HI);
-
-  SHOW_RAMDAC0_REG(NV_RAMDAC_FP_CONTROL);
-  SHOW_RAMDAC0_REG(NV_RAMDAC_GENERAL_CONTROL);
-  SHOW_RAMDAC0_REG(NV_RAMDAC_NVPLL);
-  SHOW_RAMDAC0_REG(NV_RAMDAC_MPLL);
-  SHOW_RAMDAC0_REG(NV_RAMDAC_VPLL);
-  SHOW_RAMDAC0_REG(NV_RAMDAC_PLL_SELECT);
-  SHOW_RAMDAC0_REG(NV_RAMDAC_VPLL2);
-
-  SHOW_RAMDAC0_REG(NV_RAMDAC_NVPLL_B);
-  SHOW_RAMDAC0_REG(NV_RAMDAC_MPLL_B);
-  SHOW_RAMDAC0_REG(NV_RAMDAC_VPLL_B);
-  SHOW_RAMDAC0_REG(NV_RAMDAC_VPLL2_B);
+  SHOW_CRTC1_REG(NV_CRTC_081C);
+  SHOW_CRTC1_REG(NV_CRTC_0830);
+  SHOW_CRTC1_REG(NV_CRTC_0834);
+
+#define SHOW_RAMDAC_REG(r) do { printf("%s0\t%08x\n", #r, radeon_get32(NV_PRAMDAC0_OFFSET+r, #r)); \
+	printf("%s1\t%08x\n", #r, radeon_get32(NV_PRAMDAC1_OFFSET+r, #r)); \
+} while(0)
+
+  SHOW_RAMDAC_REG(NV_RAMDAC_CURSOR_POS);
+  SHOW_RAMDAC_REG(NV_RAMDAC_CURSOR_CTRL);
+  SHOW_RAMDAC_REG(NV_RAMDAC_CURSOR_DATA_LO);
+  SHOW_RAMDAC_REG(NV_RAMDAC_CURSOR_DATA_HI);
+  SHOW_RAMDAC_REG(NV_RAMDAC_0404);
+
+  SHOW_RAMDAC_REG(NV_RAMDAC_FP_CONTROL);
+  SHOW_RAMDAC_REG(NV_RAMDAC_GENERAL_CONTROL);
+  SHOW_RAMDAC_REG(NV_RAMDAC_NVPLL);
+  SHOW_RAMDAC_REG(NV_RAMDAC_MPLL);
+  SHOW_RAMDAC_REG(NV_RAMDAC_VPLL);
+  SHOW_RAMDAC_REG(NV_RAMDAC_PLL_SELECT);
+  SHOW_RAMDAC_REG(NV_RAMDAC_VPLL2);
+
+  SHOW_RAMDAC_REG(NV_RAMDAC_NVPLL_B);
+  SHOW_RAMDAC_REG(NV_RAMDAC_MPLL_B);
+  SHOW_RAMDAC_REG(NV_RAMDAC_VPLL_B);
+  SHOW_RAMDAC_REG(NV_RAMDAC_VPLL2_B);
   
   dump_vga_regs(0);
   dump_vga_regs(1);