diff options
author | Alex Deucher <alexdeucher@gmail.com> | 2006-12-02 09:15:09 +1100 |
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committer | airlied <airlied@linux.ie> | 2006-12-02 09:15:09 +1100 |
commit | a55717ba4dd74361737210ddca00ede03830c66e (patch) | |
tree | 8187d20a8587bb6c74e65173ef4b9cd233c186ae | |
parent | e2bf24ec0994d3f0988ae9d6fa531a32683e7878 (diff) |
add tv-out registers
-rw-r--r-- | radeon_reg.h | 101 | ||||
-rw-r--r-- | radeontool.c | 30 |
2 files changed, 131 insertions, 0 deletions
diff --git a/radeon_reg.h b/radeon_reg.h index f0465af..15df09d 100644 --- a/radeon_reg.h +++ b/radeon_reg.h @@ -1768,5 +1768,106 @@ #define RADEON_CP_VC_CNTL_NUM_SHIFT 16 #define RADEON_ISYNC_CNTL 0x1724 + +#define RADEON_TV_MASTER_CNTL 0x0800 +# define RADEON_TV_ASYNC_RST (1 << 0) +# define RADEON_CRT_ASYNC_RST (1 << 1) +# define RADEON_RESTART_PHASE_FIX (1 << 3) +# define RADEON_TV_FIFO_ASYNC_RST (1 << 4) +# define RADEON_VIN_ASYNC_RST (1 << 5) +# define RADEON_AUD_ASYNC_RST (1 << 6) +# define RADEON_DVS_ASYNC_RST (1 << 7) +# define RADEON_CRT_FIFO_CE_EN (1 << 9) +# define RADEON_TV_FIFO_CE_EN (1 << 10) +# define RADEON_TVCLK_ALWAYS_ONb (1 << 30) +# define RADEON_TV_ON (1 << 31) +#define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888 +# define RADEON_Y_RED_EN (1 << 0) +# define RADEON_C_GRN_EN (1 << 1) +# define RADEON_CMP_BLU_EN (1 << 2) +# define RADEON_DAC_DITHER_EN (1 << 3) +# define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4) +# define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8) +# define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12) +# define RADEON_TV_FORCE_DAC_DATA_SHIFT 16 +#define RADEON_TV_RGB_CNTL 0x0804 +# define RADEON_SWITCH_TO_BLUE (1 << 4) +# define RADEON_RGB_DITHER_EN (1 << 5) +# define RADEON_RGB_SRC_SEL_MASK (3 << 8) +# define RADEON_RGB_SRC_SEL_CRTC1 (0 << 8) +# define RADEON_RGB_SRC_SEL_RMX (1 << 8) +# define RADEON_RGB_SRC_SEL_CRTC2 (2 << 8) +# define RADEON_RGB_CONVERT_BY_PASS (1 << 10) +# define RADEON_TVOUT_SCALE_EN (1 << 26) +#define RADEON_TV_SYNC_CNTL 0x0808 +#define RADEON_TV_HTOTAL 0x080c +#define RADEON_TV_HDISP 0x0810 +#define RADEON_TV_HSTART 0x0818 +#define RADEON_TV_HCOUNT 0x081C +#define RADEON_TV_VTOTAL 0x0820 +#define RADEON_TV_VDISP 0x0824 +#define RADEON_TV_VCOUNT 0x0828 +#define RADEON_TV_FTOTAL 0x082c +#define RADEON_TV_FCOUNT 0x0830 +#define RADEON_TV_FRESTART 0x0834 +#define RADEON_TV_HRESTART 0x0838 +#define RADEON_TV_VRESTART 0x083c +#define RADEON_TV_HOST_READ_DATA 0x0840 +#define RADEON_TV_HOST_WRITE_DATA 0x0844 +#define RADEON_TV_HOST_RD_WT_CNTL 0x0848 +# define RADEON_HOST_FIFO_RD (1 << 12) +# define RADEON_HOST_FIFO_RD_ACK (1 << 13) +# define RADEON_HOST_FIFO_WT (1 << 14) +# define RADEON_HOST_FIFO_WT_ACK (1 << 15) +#define RADEON_TV_VSCALER_CNTL1 0x084c +# define RADEON_RESTART_FIELD (1 << 29) /* restart on field 0 */ +# define RADEON_Y_DEL_W_SIG_SHIFT 26 +#define RADEON_TV_TIMING_CNTL 0x0850 +#define RADEON_TV_VSCALER_CNTL2 0x0854 +# define RADEON_DITHER_MODE (1 << 0) +# define RADEON_Y_OUTPUT_DITHER_EN (1 << 1) +# define RADEON_UV_OUTPUT_DITHER_EN (1 << 2) +# define RADEON_UV_TO_BUF_DITHER_EN (1 << 3) +#define RADEON_TV_Y_FALL_CNTL 0x0858 +# define RADEON_Y_FALL_PING_PONG (1 << 16) +#define RADEON_TV_Y_RISE_CNTL 0x085c +# define RADEON_Y_RISE_PING_PONG (1 << 16) +#define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860 +#define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864 +# define RADEON_YUPSAMP_EN (1 << 0) +# define RADEON_UVUPSAMP_EN (1 << 2) +#define RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868 +#define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c +#define RADEON_TV_MODULATOR_CNTL1 0x0870 +# define RADEON_YFLT_EN (1 << 2) +# define RADEON_UVFLT_EN (1 << 3) +# define RADEON_ALT_PHASE_EN (1 << 6) +# define RADEON_SYNC_TIP_LEVEL (1 << 7) +# define RADEON_SLEW_RATE_LIMIT (1 << 23) +#define RADEON_TV_MODULATOR_CNTL2 0x0874 +#define RADEON_TV_CRC_CNTL 0x0890 +#define RADEON_TV_UV_ADR 0x08ac +# define RADEON_MAX_UV_ADR_MASK 0x000000ff +# define RADEON_MAX_UV_ADR_SHIFT 0 +# define RADEON_TABLE1_BOT_ADR_MASK 0x0000ff00 +# define RADEON_TABLE1_BOT_ADR_SHIFT 8 +# define RADEON_TABLE3_TOP_ADR_MASK 0x00ff0000 +# define RADEON_TABLE3_TOP_ADR_SHIFT 16 +# define RADEON_HCODE_TABLE_SEL_MASK 0x06000000 +# define RADEON_HCODE_TABLE_SEL_SHIFT 25 +# define RADEON_VCODE_TABLE_SEL_MASK 0x18000000 +# define RADEON_VCODE_TABLE_SEL_SHIFT 27 +# define RADEON_TV_MAX_FIFO_ADDR 0x1a7 +# define RADEON_TV_MAX_FIFO_ADDR_INTERNAL 0x1ff +#define RADEON_TV_PLL_FINE_CNTL 0x0020 /* PLL */ +#define RADEON_TV_PLL_CNTL 0x0021 /* PLL */ +# define RADEON_TV_SLIP_EN (1 << 23) +# define RADEON_TV_DTO_EN (1 << 28) +#define RADEON_TV_PLL_CNTL1 0x0022 /* PLL */ +# define RADEON_TVPLL_TEST_DIS (1 << 31) +# define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30) +# define RADEON_TVPLL_SLEEP (1 << 3) +# define RADEON_TVPLL_REFCLK_SEL (1 << 4) +#define RADEON_GPIOPAD_A 0x019c #endif diff --git a/radeontool.c b/radeontool.c index af43a92..e7cbf00 100644 --- a/radeontool.c +++ b/radeontool.c @@ -588,6 +588,36 @@ static struct { REGLIST(TMDS_PLL_CNTL), REGLIST(TMDS_TRANSMITTER_CNTL), REGLIST(ISYNC_CNTL), + REGLIST(TV_MASTER_CNTL), + REGLIST(TV_PRE_DAC_MUX_CNTL), + REGLIST(TV_RGB_CNTL), + REGLIST(TV_SYNC_CNTL), + REGLIST(TV_HTOTAL), + REGLIST(TV_HDISP), + REGLIST(TV_HSTART), + REGLIST(TV_HCOUNT), + REGLIST(TV_VTOTAL), + REGLIST(TV_VDISP), + REGLIST(TV_VCOUNT), + REGLIST(TV_FTOTAL), + REGLIST(TV_FCOUNT), + REGLIST(TV_FRESTART), + REGLIST(TV_HRESTART), + REGLIST(TV_VRESTART), + REGLIST(TV_VSCALER_CNTL1), + REGLIST(TV_TIMING_CNTL), + REGLIST(TV_VSCALER_CNTL2), + REGLIST(TV_Y_FALL_CNTL), + REGLIST(TV_Y_RISE_CNTL), + REGLIST(TV_Y_SAW_TOOTH_CNTL), + REGLIST(TV_UPSAMP_AND_GAIN_CNTL), + REGLIST(TV_GAIN_LIMIT_SETTINGS), + REGLIST(TV_LINEAR_GAIN_SETTINGS), + REGLIST(TV_MODULATOR_CNTL1), + REGLIST(TV_MODULATOR_CNTL2), + REGLIST(TV_CRC_CNTL), + REGLIST(TV_UV_ADR), + REGLIST(GPIOPAD_A), }; void radeon_reg_match(const char *pattern) |