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2013-10-06Add support for decoding cache information in cpuid.4HEADmasterSøren Sandmann Pedersen1-0/+59
When cpuid.2 reports a cache descriptor of 0xff, that means cpuid.2 doesn't contain any information about caches and that instead you are supposed to find this information in cpuid.4. This patch adds support for decoding that information.
2013-05-23Add support for cache descriptor 0x76Søren Sandmann Pedersen1-0/+1
This corresponds to an ITLB for 2M/4M pages with 8 entries.
2013-04-01Make the l2l3/l3l2 tables only contain the common values.Dave Jones1-9/+9
Should solve https://bugzilla.redhat.com/show_bug.cgi?id=928889
2011-12-28Fix logic bug spotted by coverityDave Jones1-3/+3
2011-08-02Add sandybridge identDave Jones1-0/+4
2011-05-29Only parse EBLCR if the MSR read succeededDave Jones1-2/+2
2011-04-21Add Westmere-EX identDave Jones1-0/+4
2011-04-05Revert "turn this back on now that we're back in beta"Dave Jones1-1/+1
This reverts commit 13601fa772f8525f208eb81914893d8204495a05. Turn it back off again. Need to do a release to fix lsmsr.
2011-03-15turn this back on now that we're back in betaDave Jones1-1/+1
2011-03-14disable this for 1.28, it's not ready.Dave Jones1-1/+1
2011-03-12Fix up the 32bit build.Dave Jones1-2/+2
Reported-by: Andre Nogueira <andre.neo.net@gmail.com>
2011-03-11Some more IDA decodingDave Jones2-2/+18
2011-03-08Start decoding IDADave Jones3-4/+52
2011-02-22gather topology info per-cpuDave Jones1-3/+3
2011-02-22Split intel info into basic/extended.Dave Jones1-3/+4
2011-02-22Fix topology parsingDave Jones2-9/+12
2011-02-22rename bluesmoke to machine_checkDave Jones3-4/+4
2011-02-18remove excessive newlines, add some where missing.Dave Jones2-4/+5
2011-02-18clean up the machine check decoding a littleDave Jones1-29/+38
2011-02-18don't display 'type' if it's reserved.Dave Jones1-10/+12
2011-02-18Split MSR-PM into thermal and performanceDave Jones4-34/+58
2011-02-18more formatting.Dave Jones1-5/+5
2011-02-18use model()Dave Jones1-1/+1
2011-02-18formatting. Print out raw values as well as decoded.Dave Jones1-9/+17
2011-02-18print thermal status raw value.Dave Jones1-5/+9
and clean up parsing
2011-02-18IA32_PERF_STATUS is model specific.Dave Jones1-22/+4
We shouldn't try to parse it using the encoding of one ancient CPU, as the results are likely to be incorrect. Just dump it raw for now. I don't particularly feel like looking up the encoding for every CPU, so this is probably how this is going to stay. For people who care, they can download the spec for their CPU and decode it by hand.
2011-01-19use MB macro, like in the kernelDave Jones1-43/+45
2011-01-19update cache descriptorsDave Jones1-6/+11
2011-01-10don't print out the brand if it's 'unsupported'Dave Jones1-14/+19
2010-10-25Add an Atom variantDave Jones1-0/+4
2010-09-29Add an Intel codename.Dave Jones1-1/+1
2010-09-22Add an atom ident.Dave Jones1-0/+4
2010-09-22Add some Nehalem core codenames.Dave Jones1-3/+18
2010-09-13Add Core i7 informational URL.Warren Turkal1-0/+3
Signed-off-by: Warren Turkal <wt@penguintechs.org>
2010-09-08Add informational URL for Pentium III Dothan.Warren Turkal1-0/+3
Signed-off-by: Warren Turkal <wt@penguintechs.org>
2009-12-10Store the number of siblings.Dave Jones1-8/+8
2009-12-10Print a summary of the information from topology discovery.Dave Jones1-7/+3
2009-12-10Make the new cpuid4 & cpuid_count functions take a cpu number integerDave Jones1-2/+2
instead of a cpudata struct so they match the other cpuid functions.
2009-12-10Intel CPU topology reworking.Dave Jones4-50/+65
This steals lots of code from the kernel, and munges it to work with userspace. In doing so, I renamed a bunch of x86info's struct cpudata members to match the kernels struct cpu_data, just to make it easier to sync any future changes.
2009-11-10PATCH: add support for new cpuid descriptorsnick black1-0/+4
While working on libtorque (http://github.com/dankamongmen/libtorque), I found several cache/TLB descriptors being missed by x86info on a Nehalem i7 server. This patch adds the missing descriptors, using Intel's 2009-06 Application Note 845 as a reference. No, the 7 entries of descriptor 0x55 are not a typo, or at least not mine. Descriptor 0xe4 still isn't picked up, despite being listed in your L3L2CACHE table. It looks like decode_intel_cache() isn't called with this table in all cases.
2009-04-08Remove ;'s from all other add_to_cpuname macros.Dave Jones3-3/+3
2009-04-08Add Intel Z515/Z550 Atoms.Dave Jones1-12/+16
(also, make add_to_cpuname not have a ; in the macro)
2009-04-03Don't read MCG_CTL if it's not presentJike Song1-4/+4
rdmsr with MCG_CTL in ecx will result a GP# if it is simply not available. The msr driver in kernel is now clever enough to deal with this problem with an exception table, but it is simply not necessary to try. lsmsr has the same prblem as x86info, but I can't figure out a nice workaround. Signed-off-by: Jike Song <albcamus@gmail.com>
2009-01-31minor cleanups.Dave Jones1-73/+75
2009-01-31Add Core i7 cache descriptors.Dave Jones1-0/+15
2009-01-14Atom series 200Dave Jones1-2/+4
2009-01-14Atom series 300Dave Jones1-2/+3
2009-01-14Atom N270 seriesDave Jones1-19/+33
2009-01-14Add Atom.Dave Jones1-0/+23
http://www.intel.com/products/atom/techdocs.htm
2009-01-14Add Nehalem.Dave Jones1-0/+19
http://download.intel.com/design/processor/specupdt/320836.pdf
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