diff options
| author | Søren Sandmann Pedersen <ssp@redhat.com> | 2013-05-23 07:49:50 -0400 |
|---|---|---|
| committer | Søren Sandmann Pedersen <ssp@redhat.com> | 2013-05-23 07:49:50 -0400 |
| commit | d1a6d2bb69b6dc549b1e3a4a54d4713263a3612e (patch) | |
| tree | 0e2203ac9e0e55f5f1c575bff1c8aecc6c2c774b | |
| parent | c09b28277213f6848ced5078b6112f29e840c26a (diff) | |
Add support for cache descriptor 0x76
This corresponds to an ITLB for 2M/4M pages with 8 entries.
| -rw-r--r-- | Intel/cachesize.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Intel/cachesize.c b/Intel/cachesize.c index 1d01c4d..cfdec55 100644 --- a/Intel/cachesize.c +++ b/Intel/cachesize.c @@ -147,6 +147,7 @@ static struct _cache_table ITLB_cache_table[] = { 0x51, 128, "Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 128 entries." }, { 0x52, 256, "Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 256 entries." }, { 0x55, 7, "Instruction TLB: 2MB or 4MB pages, fully associative, 7 entries" }, + { 0x76, 8, "Instruction TLB: 2M/4M pages, fully associative, 8 entries" }, { 0xb0, 128, "Instruction TLB: 4K pages, 4-way associative, 128 entries." }, { 0xb1, 4, "Instruction TLB: 4x 4MB page entries, or 8x 2MB pages entries, 4-way associative" }, { 0xb2, 64, "Instruction TLB: 4K pages, 4-way associative, 64 entries." }, |