diff options
author | Dave Jones <davej@redhat.com> | 2013-04-01 19:19:36 -0400 |
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committer | Dave Jones <davej@redhat.com> | 2013-04-01 19:19:36 -0400 |
commit | c09b28277213f6848ced5078b6112f29e840c26a (patch) | |
tree | 2206827cc01eb676b89dd3f24412416f4eb93897 | |
parent | 4eb2d29e9d9abd715e4191babfe81990f08a6dcd (diff) |
Make the l2l3/l3l2 tables only contain the common values.
Should solve https://bugzilla.redhat.com/show_bug.cgi?id=928889
-rw-r--r-- | Intel/cachesize.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/Intel/cachesize.c b/Intel/cachesize.c index 7ab124a..1d01c4d 100644 --- a/Intel/cachesize.c +++ b/Intel/cachesize.c @@ -112,6 +112,15 @@ static struct _cache_table L3L2_cache_table[] = { 0x4c, MB(12), "L3 cache: 12MB, 12-way associative. 64 byte line size." }, { 0x4d, MB(16), "L3 cache: 16MB, 16-way associative. 64 byte line size." }, { 0x78, MB(1), "L3 cache: 1MB, sectored, 8-way associative. 64 byte line size." }, + { 0, 0, NULL } +}; + +static struct _cache_table L3_cache_table[] = +{ + { 0x22, 512, "L3 cache: 512KB, 4-way associative. 64 byte line size." }, + { 0x23, MB(1), "L3 cache: 1MB, 8-way associative. 64 byte line size." }, + { 0x25, MB(2), "L3 cache: 2MB, 8-way associative. 64 byte line size." }, + { 0x29, MB(4), "L3 cache: 4MB, 8-way associative. 64 byte line size." }, { 0xd0, 512, "L3 cache: 512KB, 4-way associative. 64 byte line size." }, { 0xd1, MB(1), "L3 cache: 1MB, 4-way associative. 64 byte line size." }, { 0xd2, MB(2), "L3 cache: 2MB, 4-way associative. 64 byte line size." }, @@ -130,15 +139,6 @@ static struct _cache_table L3L2_cache_table[] = { 0, 0, NULL } }; -static struct _cache_table L3_cache_table[] = -{ - { 0x22, 512, "L3 cache: 512KB, 4-way associative. 64 byte line size." }, - { 0x23, MB(1), "L3 cache: 1MB, 8-way associative. 64 byte line size." }, - { 0x25, MB(2), "L3 cache: 2MB, 8-way associative. 64 byte line size." }, - { 0x29, MB(4), "L3 cache: 4MB, 8-way associative. 64 byte line size." }, - { 0, 0, NULL } -}; - static struct _cache_table ITLB_cache_table[] = { { 0x1, 32, "Instruction TLB: 4KB pages, 4-way associative, 32 entries" }, |